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19-4443; Rev 0; 2/09
KIT ATION EVALU BLE AVAILA
AMD 2-/3-Output Mobile Serial VID Controller
General Description Features
o Dual-Output Fixed-Frequency Core Supply Controller Split or Combinable Outputs Detected at Power-Up Dynamic Phase Selection Optimizes Active/Sleep Efficiency Transient Phase Repeat Reduces Output Capacitance True Out-of-Phase Operation Reduces Input Capacitance Programmable AC and DC Droop Accurate Current Balance and Current Limit Integrated Drivers for Large SynchronousRectifier MOSFETs Programmable 100kHz to 600kHz Switching Frequency 4V to 26V Battery Input Voltage Range o 4A Internal Switch Northbridge SMPS 2.7V to 5.5V Input Voltage Range 2x Programmable Switching Frequency 75m/40m Power Switches o 0.5% VOUT Accuracy over Line, Load, and Temperature o AMD SVI-Compliant Serial Interface with Switchable Address o 7-Bit On-Board DAC: 0 to +1.550V Output Adjust Range o Integrated Boost Switches o Adjustable Slew-Rate Control o Power-Good (PWRGD) and Thermal-Fault (VRHOT) Outputs o System Power-OK (PGD_IN) Input o Overvoltage, Undervoltage, and Thermal-Fault Protection o Voltage Soft-Startup and Passive Shutdown o < 1A Typical Shutdown Current
MAX17480
The MAX17480 is a triple-output, step-down, fixedfrequency controller for AMD's serial VID interface (SVI) CPU and northbridge (NB) core supplies. The MAX17480 consists of two high-current SMPSs for the CPU cores and one 4A internal switch SMPS for the NB core. The two CPU core SMPSs run 180 out-of-phase for true interleaved operation, minimizing input capacitance. The 4A internal switch SMPS runs at twice the switching frequency of the core SMPS, reducing the size of the external components. The MAX17480 is fully AMD SVI compliant. Output voltages are dynamically changed through a 2-wire SVI, allowing the SMPSs to be individually programmed to different voltages. A slew-rate controller allows controlled transitions between VID codes and controlled soft-start. SVI also allows each SMPS to be individually set into a low-power pulse-skipping state. Transient phase repeat improves the response of the fixed-frequency architecture, reducing the total output capacitance for the CPU core. A thermistor-based temperature sensor provides a programmable thermal-fault output (VRHOT). The MAX17480 includes output overvoltage protection (OVP), undervoltage protection (UVP), and thermal protection. When any of these protection features detect a fault, the controller shuts down. True differential current sensing improves current limit and load-line accuracy. The MAX17480 has an adjustable switching frequency, allowing 100kHz to 600kHz operation per core SMPS, and twice that for the NB SMPS.
Applications
Mobile AMD SVI Core Supplies Multiphase CPU Core Supplies Voltage-Positioned, Step-Down Converters Notebook/Desktop Computers
Ordering Information
PART TEMP RANGE PIN-PACKAGE MAX17480GTL+ -40C to +105C 40 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
ABSOLUTE MAXIMUM RATINGS
(Note 1) VDD, VIN3, VCC, VDDIO to AGND ..............................-0.3V to +6V LX2 to BST2..............................................................-6V to +0.3V PWRGD to AGND .....................................................-0.3V to +6V LX3 to PGND (Note 2) ..............................................-0.6V to +6V SHDN to AGND ........................................................-0.3V to +6V DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) GNDS1, GNDS2, THRM, VRHOT to AGND..............-0.3V to +6V DL1 to PGND ..............................................-0.3V to (VDD + 0.3V) CSP_, CSN_, ILIM12 to AGND .................................-0.3V to +6V DL2 to PGND ..............................................-0.3V to (VDD + 0.3V) SVC, SVD, PGD_IN to AGND ...................................-0.3V to +6V Continuous Power Dissipation (TA = +70C) FBDC_, FBAC_, OUT3 to AGND ..............................-0.3V to +6V 40-Pin TQFN (derate 22.2mW/C above +70C) .......1778mW OSC, TIME, OPTION, ILIM3 to AGND ........-0.3V to (VCC + 0.3V) BST1, BST2 to AGND .............................................-0.3V to +36V Operating Temperature Range .........................-40C to +105C BST1, BST2 to VDD .................................................-0.3V to +30V Junction Temperature ......................................................+150C BST3 to AGND...................................(VDD - 0.3V) to (VLX3 + 6V) Storage Temperature Range .............................-65C to +150C LX1 to BST1..............................................................-6V to +0.3V Lead Temperature (soldering, 10s) .................................+300C LX3 RMS Current (Note 2) .....................................................4A Note 1: Absolute Maximum Ratings measured with 20MHz scope bandwidth. Note 2: LX3 has clamp diodes to PGND and IN3. If continuous current is applied through these diodes, thermal limits must be observed.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INPUT SUPPLIES VIN Input Voltage Range VBIAS VIN3 VDDIO VCC Undervoltage-Lockout Threshold VCC Power-On Reset Threshold VDDIO Undervoltage-Lockout Threshold VIN3 Undervoltage-Lockout Threshold Quiescent Supply Current (VCC) Quiescent Supply Currents (VDD) Quiescent Supply Current (VDDIO) Quiescent Supply Current (IN3) Shutdown Supply Current (VCC) ICC IDD IDDIO I IN3 Skip mode, OUT3 forced above its regulation point SHDN = GND, TA = +25C VUVLO VCC rising, 50mV typical hysteresis, latched, UV fault Falling edge, typical hysteresis = 1.1V, faults cleared and DL_ forced high when VCC falls below this level VDDIO rising, 100mV typical hysteresis, latched, UV fault VIN3 rising, 100mV typical hysteresis Skip mode, FBDC_ and OUT3 forced above their regulation points Skip mode, FBDC_ and OUT3 forced above their regulation points, TA = +25C 0.7 2.5 Drain of external high-side MOSFET VCC, VDD 4 4.5 2.7 1.0 4.10 4.25 26 5.5 5.5 2.7 4.45 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
1.8
V
0.8 2.6 5 0.01 10 50 0.01
0.9 2.7 10 1 25 200 1
V V mA A A A A
2
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AMD 2-/3-Output Mobile Serial VID Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Shutdown Supply Currents (VDD) Shutdown Supply Current (VDDIO) Shutdown Supply Current (IN3) SYMBOL CONDITIONS SHDN = GND, TA = +25C SHDN = GND, TA = +25C SHDN = GND, TA = +25C Measured at FBDC_ for the core SMPSs; measured at OUT3 for the NB SMPS; 30% duty cycle, no load, ILIM3 = VCC, VOUT3 = VDAC3 + 12.5mV (Note 3) MIN TYP 0.01 0.01 0.01 MAX 1 1 1 UNITS A A A
MAX17480
INTERNAL DACs, SLEW RATE, PHASE SHIFT DAC codes from 0.8375V to 1.5500V DAC codes from 0.5000V to 0.8250V DAC codes from 12.5mV to 0.4875V -0.5 +0.5 %
DC Output Voltage Accuracy (Note 1)
VOUT
-5
+5 mV
-10 12.5
+10 mV % Degrees % +10 +15 1 % mV/s +3 +250 +7 % A nA
OUT3 Offset SMPS1 to SMPS2 Phase Shift SMPS3 to SMPS1 and SMPS2 Phase Shift SMPS2 starts after SMPS1 SMPS3 starts after SMPS1 or SMPS2 RTIME = 143k , SR = 6.25mV/s During transition RTIME = 35.7k to 357k , SR = 25mV/s to 2.5mV/s Startup FBAC_ Input Bias Current FBDC_ Input Bias Current IFBAC_ IFBDC_ CSP_ = CSN_, TA = +25C TA = +25C R OSC = 143k (f OSC1 = f OSC2 = 300kHz nominal, f OSC3 = 600kHz nominal) R OSC = 71.4k (f OSC1 = f OSC2 = 600kHz nominal, f OSC3 = 1.2MHz nominal) to 432k (fOSC1 = f OSC2 = 99kHz nominal, f OSC3 = 199kHz nominal) Either SMPS, PWM mode, droop disabled; zero to full load Either SMPS, 4V < VIN < 26V VGNDS_ A GNDS_ I GNDS _ Separate mode Separate: VOUT_/ VGNDS_, -200mV VGNDS_ +200mV; combined: VOUT/ VGNDS_, -200mV VGNDS_ +200mV TA = +25C -200 0.95 -2 -3 -250 -7 -10 -15
50 180 25
Slew-Rate Accuracy
Switching Frequency Accuracy
f OSC1, f OSC2, f OSC3
-9
+9
SMPS1 AND SMPS2 CONTROLLERS DC Load Regulation Line Regulation Error GNDS_ Input Range GNDS_ Gain GNDS_ Input Bias Current -0.1 0.03 +200 1.00 1.05 +2 % %/V mV V/V A
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Combined-Mode Detection Threshold Maximum Duty Factor Minimum On-Time Current-Limit Threshold Tolerance Zero-Crossing Threshold Idle ModeTM Threshold CS_ Input Leakage Current CS_ Common-Mode Input Range AC Droop and Current Balance Amplifier Transconductance AC Droop and Current Balance Amplifier Offset No-Load Positive Offset Transient Detection Threshold DMAX t ONMIN VCSP_ - VCSN _ = 0.052 x (VREF - VILIM), (VREF - VILM) = 0.2V to 1.0V VGND_ - VLX_, skip mode VCSP_ - VCSN _, skip mode, 0.15 x VLIMIT CSP_ and CSN_, TA = +25C CSP_ and CSN_ IFBAC_/( VCS_), VFBAC _ = VCSN _ = 1.2V, VCSP_ - VCSN _ = 0 to +40mV IFBAC_/Gm(FBAC_) OPTION = 2V or GND Measured at FBDC_ with respect to steady-state FBDC_ regulation voltage, 10mV hysteresis (typ) -47 -2 -0.2 0 SYMBOL CONDITIONS GNDS1, GNDS2, detection after REFOK, latched, cleared by cycling SHDN MIN 0.7 90 TYP 0.8 92 150 MAX 0.9 UNITS V % ns
SMPS1 AND SMPS2 CURRENT LIMIT VLIMIT VZX VIMIN -3 1 +2 +0.2 2 +3 mV mV mV A V
SMPS1 AND SMPS2 DROOP, CURRENT BALANCE, AND TRANSIENT RESPONSE Gm(FBAC_) 1.94 -1.5 +12.5 -41 -33 2.00 2.06 +1.5 mS mV mV mV
SMPS3 INTERNAL 4A STEP-DOWN CONVERTER OUT3 Load Regulation OUT3 Line Regulation OUT3 Input Current LX3 Leakage Current Internal MOSFET On-Resistance LX3 Peak Current Limit LX3 Idle-Mode Trip Level LX3 Zero-Crossing Trip Level Maximum Duty Factor Minimum On-Time I OUT3 ILX3 R ON(NH3) R ON(NL3) ILX3PK ILX3MIN I ZX3 DMAX t ONMIN RDROOP3 0 to 100% duty cycle TA = +25C SHDN = GND, VLX3 = GND or 5.5V, VIN3 = 5.5V, TA = +25C High-side n-channel Low-side n-channel ILIM3 = VCC ILIM3 = GND Percentage of ILX3PK Skip mode 84 4.75 3.75 -100 -20 75 40 5.25 4.25 25 20 87 150 4 5.5 5 -5 +100 +20 150 75 6 5 % mA % ns 7 mV/A mV nA A m A
Idle Mode is a trademark of Maxim Integrated Products, Inc.
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER FAULT DETECTION PWM mode Output Overvoltage Trip Threshold (SMPS1 and SMPS2 Only) Measured at FBDC_, rising edge Skip mode and output has not reached the regulation voltage Minimum OVP threshold Output Overvoltage Fault Propagation Delay (SMPS1 and SMPS2 Only) Output Undervoltage Protection Trip Threshold Output Undervoltage Fault Propagation Delay t OVP FBDC_ forced 25mV above trip threshold Measured at FBDC_ or OUT3 with respect to unloaded output voltage FBDC_ forced 25mV below trip threshold Measured at FBDC_ or OUT3 with respect to unloaded output voltage,15mV hysteresis (typ) t PWRGD Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage) 250 1.80 300 1.85 350 1.90 V 0.8 mV SYMBOL CONDITIONS MIN TYP MAX UNITS
VOVP_
10
s
VUVP tUVP
-450
-400 10
-350
mV s
-350
-300
-250 mV
PWRGD Threshold
+150
+200
+250
PWRGD Propagation Delay PWRGD, Output Low Voltage PWRGD Leakage Current PWRGD Startup Delay and Transition Blanking Time VRHOT Trip Threshold VRHOT Delay VRHOT, Output Low Voltage VRHOT Leakage Current THRM Input Leakage Thermal-Shutdown Threshold GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance
FBDC_ or OUT3 forced 25mV outside the PWRGD trip thresholds I SINK = 4mA High state, PWRGD forced to 5.5V, TA = +25C Measured from the time when FBDC_ and OUT3 reach the target voltage Measured at THRM, with respect to VCC, falling edge, 115mV hysteresis (typ) 29.5
10 0.4 1 20 30 10 0.4 1 -100 +160 +100 30.5
s V A s % S V A nA C 2.5 2.5 2.0 0.6
I PWRGD tBLANK
t VRHOT
THRM forced 25mV below the VRHOT trip threshold, falling edge I SINK = 4mA High state, VRHOT forced to 5V, TA = +25C TA = +25C
T SHDN
Hysteresis = 15C BST_ - LX_ forced to 5V (Note 4) DL_, high state DL_, low state High state (pullup) Low state (pulldown)
R ON(DH _) R ON(DL_)
0.9 0.7 0.7 0.25
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DH_ Gate-Driver Source/Sink Current DL_ Gate-Driver Source Current DL_ Gate-Driver Sink Current Dead Time Internal BST1, BST2 Switch RON Internal BST3 Switch R ON 2-WIRE I2C BUS LOGIC INTERFACE SVI Logic-Input Current SVI Logic-Input Threshold SVC Clock Frequency START Condition Hold Time Repeated START Condition Setup Time STOP Condition Setup Time f SVC tHD;STA t SU;STA t SU;STO A master device must internally provide a hold time of at least 300ns for the SVD signal (referred to the VIHMIN of SVC signal) to bridge the undefined region of SVC's falling edge 10 160 Measured from 10% to 90% of VDDIO Input filters on SVD and SVC suppress noise spike less than 50ns 20 SHDN, PGD_IN, TA = +25C ILIM3, OPTION, TA = +25C SHDN, rising edge, hysteresis = 225mV High, OPTION, ILIM3 Input Logic Levels 3.3V, OPTION 2V, OPTION Low, OPTION, ILIM3 PGD_IN Logic-Input Threshold PGD_IN, rising edge, hysteresis = 65mV 0.3 x VDDIO -1 -200 0.8 VCC 0.4 2.75 1.65 3.85 2.35 0.4 0.7 x VDDIO V V +1 +200 2.0 60 40 160 160 160 SVC, SVD, TA = +25C SVC, SVD, rising edge, hysteresis 0.14 x VDDIO (V) -1 0.3 x VDDIO +1 0.7 x VDDIO 3.4 A V MHz ns ns ns SYMBOL IDH_ IDL_ tDH_DL tDL_DH CONDITIONS DH_ forced to 2.5V, BST_ - LX_ forced to 5V DL_ forced to 2.5V DH_ low to DL_ high DL_ low to DH_ high BST1, BST2 to VDD, IBST1 = IBST2 = 10mA BST3 to VDD, IBST3 = 10mA 9 9 MIN TYP 2.2 2.7 8 20 20 10 10 35 35 20 20 MAX UNITS A A A ns
IDL_ (SINK) DL_ forced to 2.5V
Data Hold
tHD;DAT
70
ns
Data Setup Time SVC Low Period SVC High Period SVC/SVD Rise and Fall Time Pulse Width of Spike Suppression INPUTS AND OUTPUTS Logic-Input Current Logic-Input Levels
t SU;DAT tLOW tHIGH tR, tF
ns ns ns ns ns A nA V
6
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AMD 2-/3-Output Mobile Serial VID Controller
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40C to +105C, unless otherwise noted. Typical values are at TA = +25C.) (Note 5)
PARAMETER INPUT SUPPLIES VIN Input Voltage Range VBIAS VIN3 VDDIO VCC Undervoltage-Lockout Threshold VDDIO Undervoltage-Lockout Threshold VIN3 Undervoltage-Lockout Threshold Quiescent Supply Current (VCC) Quiescent Supply Current Quiescent Supply Current (IN3) ICC IDDIO I IN3 Skip mode, OUT3 forced above its regulation point VUVLO VCC rising, 50mV typical hysteresis, latched, UV fault VDDIO rising, 100mV typical hysteresis, latched, UV fault VIN3 rising, 100mV typical hysteresis Skip mode, FBDC_ and OUT3 forced above their regulation points Drain of external high-side MOSFET VCC, VDD 4 4.5 2.7 1.0 4.10 0.7 2.5 26 5.5 5.5 2.7 4.45 0.9 2.7 10 25 200 V V V mA A A V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX17480
INTERNAL DACs, SLEW RATE, PHASE SHIFT Measured at FBDC_ for the core SMPSs; measured at OUT3 for the NB SMPS; 30% duty cycle, no load, ILIM3 = VCC, VOUT3 = VDAC3 + 12.5mV (Note 3) DAC codes from 0.8375V to 1.5500V DAC codes from 0.5000V to 0.8250V DAC codes from 12.5mV to 0.4875V RTIME = 143k , SR = 6.25mV/s Slew-Rate Accuracy During transition RTIME = 35.7k to 357k , SR = 25mV/s to 2.5mV/s -0.7 +0.7 %
DC Output Voltage Accuracy
VOUT
-7.5
+7.5 mV
-15
+15
-10
+10 %
-15
+15
Switching Frequency Accuracy
f OSC1, f OSC2, f OSC3
R OSC = 143k (fOSC1 = f OSC2 = 300kHz nominal, f OSC3 = 600kHz nominal) R OSC = 71.4k (f OSC1 = f OSC2 = 600kHz nominal, f OSC3 = 1.2MHz nominal) to 432k (f OSC1 = f OSC2 = 99kHz nominal, f OSC3 = 199kHz nominal)
-9
+9 %
-12
+12
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40C to +105C, unless otherwise noted. Typical values are at TA = +25C.) (Note 5)
PARAMETER GNDS_ Input Range GNDS_ Gain Combined-Mode Detection Threshold Maximum Duty Factor Minimum On-Time Current-Limit Threshold Tolerance Idle-Mode Threshold Tolerance CS_ Common-Mode Input Range DMAX t ONMIN VCSP_ - VCSN _ = 0.052 x (VREF - VILIM), (VREF - VILM) = 0.2V to 1.0V VCSP_ - VCSN _, skip mode, 0.15 x VLIMIT CSP_ and CSN_ SYMBOL VGNDS_ A GNDS_ CONDITIONS Separate mode Separate: VOUT_/ VGNDS_, -200mV VGNDS_ +200mV; combined; VOUT/ VGNDS_, -200mV VGNDS_ +200mV GNDS1, GNDS2, detection after REFOK, latched, cleared by cycling SHDN MIN -200 0.95 TYP MAX +200 1.05 UNITS mV V/V
SMPS1 AND SMPS2 CONTROLLERS
0.7 90
0.9
V %
150
ns
SMPS1 AND SMPS2 CURRENT LIMIT VLIMIT VIMIN -3 -2 0 +3 +2 2 mV mV V
SMPS1 AND SMPS2 DROOP, CURRENT BALANCE, AND TRANSIENT RESPONSE AC Droop and Current Balance Amplifier Transconductance AC Droop and Current Balance Amplifier Offset Transient Detection Threshold Gm(FBAC_) IFBAC_/( VCS_), VFBAC _ = VCSN _ = 1.2V, VCSP_ - VCSN _ = 0 to +40mV IFBAC_/Gm(FBAC_) Measured at FBDC_ with respect to steady-state FBDC_ regulation voltage, 10mV hysteresis (typ) 1.94 -1.5 2.06 +2.0 mS mV
-47
-33
mV
SMPS3 INTERNAL 4A STEP-DOWN CONVERTER OUT3 Load Regulation Internal MOSFET On-Resistance LX3 Peak Current Limit Maximum Duty Factor Minimum On-Time RDROOP3 R ON(NH3) R ON(NL3) ILX3PK DMAX t ONMIN High-side n-channel Low-side n-channel ILIM3 = VCC, skip mode 4.75 84 150 4 7 150 75 6 mV/A m A % ns
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AMD 2-/3-Output Mobile Serial VID Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40C to +105C, unless otherwise noted. Typical values are at TA = +25C.) (Note 5)
PARAMETER FAULT DETECTION PWM mode Output Overvoltage Trip Threshold (SMPS1 and SMPS2 Only) VOVP_ Measured at FBDC_, rising edge Skip mode and output have not reached the regulation voltage 250 350 mV SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX17480
1.80
1.90
V
Output Undervoltage Protection Trip Threshold
VUVP
Measured at FBDC_ or OUT3 with respect to unloaded output voltage Measured at FBDC_ or OUT3 with respect to unloaded output voltage, 15mV hysteresis (typ) I SINK = 4mA Measured at THRM, with respect to VCC, falling edge, 115mV hysteresis (typ) I SINK = 4mA BST_ - LX_ forced to 5V (Note 4) DL_, high state DL_, low state DH_ low to DL_ high DL_ low to DH_ high BST1, BST2 to VDD, IBST1 = IBST2 = 10mA BST3 to VDD, IBST3 = 10mA SVC, SVD, rising edge, hysteresis = 0.14 x VDDIO(V) High state (pullup) Low state (pulldown) Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage)
-450
-350
mV
-350
-250 mV
PWRGD Threshold
+150
+250 0.4 V % V
PWRGD, Output Low Voltage VRHOT Trip Threshold VRHOT, Output Low Voltage GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance Dead Time Internal BST1, BST2 Switch RON Internal BST3 Switch R ON 2-WIRE I2C BUS LOGIC INTERFACE SVI Logic-Input Threshold SVC Clock Frequency START Condition Hold Time Repeated START Condition Setup Time STOP Condition Setup Time f SVC t SU;STA t SU;STA t SU;STO R ON(DH _) R ON(DL_) tDH_DL tDL_DH
29.5
30.5 0.4 2.5 2.5 2.0 0.6
9 9
35 35 20 20
ns
0.3 x VDDIO 160 160 160
0.7 x VDDIO 3.4
V MHz ns ns ns
Data Hold
tHD;DAT
A master device must internally provide a hold time of at least 300ns for the SVD signal (referred to the VIHMIN of SVC signal) to bridge the undefined region of SVC's falling edge
70
ns
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40C to +105C, unless otherwise noted. Typical values are at TA = +25C.) (Note 5)
PARAMETER Data Setup Time SVC Low Period SVC High Period SVC/SVD Rise and Fall Time INPUTS AND OUTPUTS Logic-Input Levels SHDN, rising edge, hysteresis = 225mV High, OPTION, ILIM3 Input Logic Levels 3.3V, OPTION 2V, OPTION Low, OPTION, ILIM3 PGD_IN Logic-Input Threshold PGD_IN, rising edge, hysteresis = 65mV 0.3 x VDDIO 0.8 VCC 0.4 2.75 1.65 3.85 2.35 0.4 0.7 x VDDIO V V 2.0 V SYMBOL t SU;DAT tLOW tHIGH tR, tF Measured from 10% to 90% of VDDIO Input filters on SVD and SVC suppress noise spike less than 50ns CONDITIONS MIN 10 160 60 40 TYP MAX UNITS ns ns ns ns
Note 3: When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error-comparator threshold by 50% of the ripple. In discontinuous conduction, the output voltage has a DC regulation level higher than the error-comparator threshold by 50% of the ripple. The core SMPSs have an integrator that corrects for this error. The NB SMPS has an offset determined by the ILIM3 pin, and a -6.5mV/A load line. Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the TQFN package. Note 5: Specifications to TA = -40C to +105C are guaranteed by design, not production tested.
tHD;STA
tR tHIGH
SVC
tLOW
tF SVD VIH VIL
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Figure 1. Timing Definitions Used in the Electrical Characteristics
10
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AMD 2-/3-Output Mobile Serial VID Controller
Typical Operating Characteristics
(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25C, unless otherwise noted.)
MAX17480
CORE SMPS 1-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 1.2V)
MAX17480 toc01
CORE SMPS 2-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 1.2V)
PWM MODE
MAX17480 toc02
CORE SMPS OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 1.2V)
VIN = 12V
MAX17480 toc03
100 7V 90 EFFICIENCY (%)
100
1.205
OUTPUT VOLTAGE (V)
90 EFFICIENCY (%) 12V
1.200 SKIP MODE AND PWM MODE
80 20V 70 SKIP MODE PWM MODE 60 0.1 1 10 100 LOAD CURRENT (A)
80 12V 70
20V
1.195
7V
60 1 10 LOAD CURRENT (A) 100
1.190 0 5 10 LOAD CURRENT (A) 15 20
CORE SMPS 1-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 0.8V)
MAX17480 toc04
CORE SMPS OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 0.8V)
MAX17480 toc05
NB SMPS EFFICIENCY vs. LOAD CURRENT (1V)
MAX17480 toc06
100 7V 90 EFFICIENCY (%) 12V
0.805 VIN = 12V
100 3.3V 90 EFFICIENCY (%)
OUTPUT VOLTAGE (V)
0.800 SKIP MODE AND PWM MODE
80 20V 70 SKIP MODE PWM MODE 60 0.1 1 10 100 LOAD CURRENT (A)
80 5V 70 SKIP MODE PWM MODE
0.795
0.790 0 5 10 LOAD CURRENT (A) 15 20
60 0.1 1 LOAD CURRENT (A) 10
NB SMPS 1V OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17480 toc07
CORE SMPS 1-PHASE SWITCHING FREQUENCY vs. LOAD CURRENT
VOUT = 1.2V
MAX17480 toc08
NB SMPS SWITCHING FREQUENCY vs. LOAD CURRENT
VOUT = 1V 700 SWITCHING FREQUENCY (kHz) 650 600 550 500 450 400 VIN = 3.3V SKIP VIN = 5V PWM VIN = 3.3V SKIP VIN = 5V PWM 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
MAX17480 toc09
1.05
350
750
SWITCHING FREQUENCY (kHz)
1.03 OUTPUT VOLTAGE (V) VIN = 5V 1.01
300 VIN = 20V SKIP VIN = 20V PWM VIN = 12V SKIP VIN = 12V PWM VIN = 7V SKIP VIN = 7V PWM
250
0.99
VIN = 3.3V
200
0.97 SKIP MODE PWM MODE 0.95 0 1 2 3 4 LOAD CURRENT (A)
150
100 0.1 1 10 100 LOAD CURRENT (A)
LOAD CURRENT (A)
______________________________________________________________________________________
11
AMD 2-/3-Output Mobile Serial VID Controller MAX17480
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25C, unless otherwise noted.)
MAXIMUM INDUCTOR CURRENT vs. INPUT VOLTAGE
MAX17480 toc10
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
MAX17480 toc11
CORE SMPS VID = 1.2V OUTPUT VOLTAGE DISTRIBUTION
80 SAMPLE PERCENTAGE (%) 70 60 50 40 30 20 10 0 1.195 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 5.45 1.205 5.50
MAX17480 toc15
VOUT = 1.2V
IIN ICC + IDD
TA = +85C TA = +25C
SAMPLE SIZE = 100
29 INDUCTOR CURRENT (A)
SUPPLY CURRENT (mA)
10 ICC + IDD 1 IIN 0.1 VOUT = 1.2V SKIP MODE PWM MODE 12 15 18 21 24
27 PEAK CURRENT 25 DC CURRENT
23
21 5.0 7.5 10.0 12.5 15.0 17.5 20.0 INPUT VOLTAGE (V)
0.01 3 6 9 INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
NB SMPS VID = 1.2V OUTPUT VOLTAGE DISTRIBUTION
MAX17480 toc13
Gm(FBAC) TRANSCONDUCTANCE DISTRIBUTION
MAX17480 toc14
NB SMPS PEAK CURRENT-LIMIT DISTRIBUTION
30 25 SAMPLE PERCENTAGE (%) 20 15 10 5 0 5.00 5.05 5.10 5.15 5.20 5.25 5.30 5.35 TA = +85C TA = +25C SAMPLE SIZE = 100 ILIM3 = VCC
70 60 SAMPLE PERCENTAGE (%) 50 40 30 20 10 0 1.195 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 1.205 TA = +85C TA = +25C SAMPLE SIZE = 100
30 25 SAMPLE PERCENTAGE (%) 20 15 10 5 0 1985 1988
+85C +25C
SAMPLE SIZE = 100
1991
1994
1997
2000
2003
2006
2009
2012
2015
OUTPUT VOLTAGE (V)
TRANSCONDUCTANCE (S)
PEAK CURRENT LIMIT (A)
12
______________________________________________________________________________________
5.40
MAX17480 toc12
31
100
90
AMD 2-/3-Output Mobile Serial VID Controller
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25C, unless otherwise noted.)
MAX17480
STARTUP WAVEFORMS
MAX17480 toc16
STARTUP SEQUENCE
MAX17480 toc17
0
SHDN, 5V/div VOUT1, 0.5V/div VOUT2, 0.5V/div VOUT3, 0.5V/div
0
SHDN, 5V/div VOUT1, 0.5V/div VOUT2, 0.5V/div VOUT3, 0.5V/div
0 0 0 0 5A 0 1A
0 PWRGD, 5V/div ILX, 5A/div 0 0 0 0 0 0 200s/div VIN = 12V VBOOT = 1V ILOAD1 = 3A ILOAD2 = 3A ILOAD3 = 0.5A VIN = 12V VBOOT = 1V VSVID = 1.2V 400s/div PWRGD, 5V/div PGD_IN, 2.5V/div SVC, 2.5V/div SVD, 2.5V/div
ILX3, 1A/div 0
SHUTDOWN WAVEFORMS
MAX17480 toc18
CORE SMPS 1-PHASE LOAD-TRANSIENT RESPONSE
MAX17480 toc19
3.3V 1.2V 1.2V 1.2V VOUT1, 0.5V/div VOUT2, 0.5V/div 5V 5V 5V 5V 100s/div VIN = 12V VSVID = 1.2V ILOAD1 = 3A ILOAD2 = 3A ILOAD3 = 0.5A VIN = 12V VOUT1 = 1.2V VOUT3, 0.5V/div DL1, 10V/div DL2, 10V/div LX3, 10V/div PWRGD, 10V/div 0 20s/div ILOAD1 = 1.5A TO 13.5A TO 1.5A PWM MODE 13.5A ILX1, 10A/div 1.5A 12V LX1, 10V/div SHDN, 5V/div 1.2V VOUT1, 50mV/div
______________________________________________________________________________________
13
AMD 2-/3-Output Mobile Serial VID Controller MAX17480
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25C, unless otherwise noted.)
CORE SMPS 1-PHASE TRANSIENT PHASE REPEAT
MAX17480 toc20
CORE SMPS 2-PHASE LOAD-TRANSIENT RESPONSE
MAX17480 toc21
1.2V
VOUT1 50mV/div
1.2V
VOUT 50mV/div
13.5A 1.5A 12V 0 2s/div VIN = 12V VOUT1 = 1.2V ILOAD1 = 1.5A TO 13.5A TO 1.5A PWM MODE ILX1 10A/div
13.5A 1.5A 13.5V LX1 10V/div 1.5A ILX2 10A/div 20s/div VIN = 12V VOUT1 = 1.2V ILOAD = 3A TO 27A TO 3A PWM MODE ILX1 10A/div
CORE SMPS 2-PHASE TRANSIENT PHASE REPEAT
MAX17480 toc22
NB SMPS LOAD-TRANSIENT RESPONSE
MAX17480 toc23
1.2V
VOUT 50mV/div
1V 3.6A
VOUT3 50mV/div
13.5A 1.5A 13.5A 1.5A ILX2 10A/div 2s/div VIN = 12V VOUT1 = 1.2V ILOAD = 3A TO 27A TO 3A PWM MODE ILX1 10A/div
ILX3 2A/div 0.4A LX3 5V/div 20s/div ILOAD3 = 0.4A TO 3.6A TO 0.4A PWM MODE
5V 0 VIN3 = 5V VOUT3 = 1V
14
______________________________________________________________________________________
AMD 2-/3-Output Mobile Serial VID Controller
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25C, unless otherwise noted.)
MAX17480
CORE SMPS OUTPUT OVERLOAD WAVEFORM (SEPARATE MODE)
MAX17480 toc24
CORE SMPS OUTPUT OVERVOLTAGE WAVEFORM (SEPARATE MODE)
MAX17480 toc25
5V SHDN, 5V/div 1.2V 5V 0 1.2V 5V 0 1.2V 5V 0 100s/div VIN = 12V VSVID = 1.2V ILOAD1 = 3A TO 40A ILOAD2 = 3A ILOAD3 = 0.5A VOUT1, 1V/div DL1, 10V/div
5V SHDN, 5V/div 1.2V VOUT1, 1V/div DL1, 10V/div 0 1.2V VOUT2, 1V/div DL2, 10V/div 5V 0 1.2V 5V 0 100s/div VIN = 12V VSVID = 1.2V ILOAD1 = NO LOAD ILOAD2 = 3A ILOAD3 = 0.5A VOUT2, 1V/div DL2, 10V/div VOUT3, 1V/div LX3, 10V/div
VOUT3, 1V/div LX3, 10V/div
DYNAMIC OUTPUT-VOLTAGE TRANSITIONS (LIGHT LOAD)
MAX17480 toc26
PGD_IN TRANSITION (LIGHT LOAD)
MAX17480 toc27
1.3V 0.6V 1.3V 0.6V 1.3V 0.6V 2.5V 2.5V
VOUT1, 0.5V/div
1.1V 0.8V 0.9V 0
VOUT, 200mV/div, VOUT3, 200mV/div
VOUT2, 0.5V/div
LX1, 20V/div LX3, 5V/div VOUT2, 200mV/div LX2, 20V/div PWRGD, 5V/div PGD_IN, 5V/div 10s/div VIN = 12V VBOOT = 1.1V VOUT1 = 0.8V VOUT2 = 1.2V VOUT3 = 0.9V
VOUT3, 0.5V/div
0 1.2V 1.1V 0 5V 0 5V 0
SVC, 2.5V/div SVD, 2.5V/div 100s/div VIN = 12V VSVID = 1.3V TO 0.6V TO 1.3V
______________________________________________________________________________________
15
AMD 2-/3-Output Mobile Serial VID Controller MAX17480
Pin Description
PIN NAME FUNCTION SMPS1 and SMPS2 Current-Limit Adjust Input. The positive current-limit threshold voltage is 0.052 times the voltage between TIME and ILIM over a 0.2V to 1.0V range of V(TIME, ILIM). The IMIN12 minimum current-limit threshold voltage in skip mode is precisely 15% of the corresponding positive current-limit threshold voltage. SMPS3 Current-Limit Adjust Input. Two-level current-limit setting for SMPS3. The ILX3MIN minimum current-limit threshold in skip mode is precisely 25% of the corresponding positive current-limit threshold. 2 ILIM3 ILIM3 VCC GND 3, 4 5, 6 7 IN3 LX3 BST3 I LX3PK (A) 5.25 4.25
1
ILIM12
Internal High-Side MOSFET Drain Connection for SMPS3. Bypass to PGND with a 10F or greater ceramic capacitor close to the IC. Inductor Connection for SMPS3. Connect LX3 to the switched side of the inductor. Boost Flying Capacitor Connection for SMPS3. An internal switch between VDD and BST3 charges the flying capacitor during the time the low-side FET is on. Active-Low Shutdown Control Input. This input cannot withstand the battery voltage. Connect to VCC for normal operation. Connect to ground to put the IC into its 1A max shutdown state. During startup, the output voltage is ramped up to the voltage set by the SVC and SVD inputs at a slew rate of 1mV/s. In shutdown, the outputs are discharged using a 20 switch through the CSN_ pins for the core SMPSs and through the OUT3 pin for the northbridge SMPS. The MAX17480 powers up to the voltage set by the two SVI bits.
8
SHDN
SVC 0 0 1 1
SVD 0 1 0 1
BOOT VOLTAGE V OUT (V) 1.1 1.0 0.9 0.8
The MAX17480 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared by a rising SHDN signal. 9 10 11 12 13 OUT3 AGND SVD SVC VDDIO Feedback Input for SMPS3. A 20 shut down. Analog Ground Serial VID Data Serial VID Clock CPU I/O Voltage (1.8V or 1.5V). Logic thresholds for SVD and SVC are relative to the voltage at VDDIO. SMPS2 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS2 internally connects to a transconductance amplifier that fine tunes the output voltage-- compensating for voltage drops from the SMPS ground to the load ground. Connect GNDS1 or GNDS2 above 0.9V combined-mode operation (unified core). When GNDS2 is pulled above 0.9V, GNDS1 is used as the remote ground-sense input. discharge FET is enabled from OUT3 to PGND when SMPS3 is
14
GNDS2
16
______________________________________________________________________________________
AMD 2-/3-Output Mobile Serial VID Controller
Pin Description (continued)
PIN NAME FUNCTION Output of the Voltage-Positioning Transconductance Amplifier for SMPS2. The RC network between this pin and the positive side of the remote-sensed output voltage sets the transient AC droop:
MAX17480
RDROOP _ AC2 =
15 FBAC2
RFBAC2 x RFBDC2 x RSENSE2 x Gm(FBAC2) RFBAC2 + RFBDC2 + RFB2 Z CFB2
where RDROOP_AC2 is the transient (AC) voltage-positioning slope that provides an acceptable trade-off between stability and load-transient response, Gm(FBAC2) = 2mS (typ), and RSENSE2 is the value of the current-sense element that is used to provide the (CSP2, CSN2) current-sense voltage, ZCFB2 is the impedance of CFB2, and FBAC2 is high impedance in shutdown. Feedback-Sense Input for SMPS2. Connect a resistor RFBDC2 between FBDC2 and the positive side of the feedback remote sense, and a capacitor from FBAC2 to couple the AC ripple from FBAC2 to FBDC2. An integrator on FBDC2 corrects for output ripple and ground-sense offset. 16 FBDC2 To enable a DC load-line less than the AC load-line, add a resistor from FBAC2 to FBDC2. To enable a DC load-line equal to the AC load-line, short FBAC2 to FBDC2. See the Core SteadyState Voltage Positioning (DC Droop) section. FBDC2 is high impedance in shutdown. Negative Current-Sense Input for SMPS2. Connect to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. A 20 discharge FET is enabled from CSN2 to PGND when the SMPS2 is shut down.
17
CSN2
18
CSP2
Positive Current-Sense Input for SMPS2. Connect to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. System Power-Good Input PGD_IN is low when SHDN first goes high. The MAX17480 decodes the two SVI bits to determine the boot voltage. The SVI bits can be changed dynamically during this time while PGD_IN remains low and PWRGD is still low.
19
PGD_IN
PGD_IN goes high after the MAX17480 reaches the boot voltage. This indicates that the SVI block is active, and the MAX17480 starts to respond to the SVI commands. The MAX17480 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared by rising SHDN. After PGD_IN has gone high, if at any time PGD_IN goes low, the MAX17480 regulates to the previously stored boot VID. The slew rate during this transition is set by the resistor between the TIME and GND pins. PWRGD follows the blanking for normal VID transition. The subsequent rising edge of PGD_IN does not change the stored VID.
______________________________________________________________________________________
17
AMD 2-/3-Output Mobile Serial VID Controller MAX17480
Pin Description (continued)
PIN NAME FUNCTION Open-Drain Power-Good Output. PWRGD is the wired-OR open-drain output of all three SMPS outputs. PWRGD is forced high impedance whenever the slew-rate controller is active (output voltage transitions). 20 PWRGD During startup, PWRGD is held low for an additional 20s after the MAX17480 reaches the startup boot voltage set by the SVC and SVD pins. The MAX17480 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared by rising SHDN. PWRGD is forced low in shutdown. When SMPS is in pulse-skipping mode, the upper PWRGD threshold comparator for the respective SMPS is blanked during a downward VID transition. The upper PWRGD threshold comparator is reenabled once the output is in regulation (Figure 6). 21 22 23 DH2 LX2 BST2 SMPS2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown. SMPS2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also used as an input to SMPS2's zero-crossing comparator. Boost Flying Capacitor Connection for the DH2 High-Side Gate Driver. An internal switch between VDD and BST2 charges the flying capacitor during the time the low-side FET is on. SMPS2 Low-Side Gate-Driver Output. DL2 swings from GND2 to VDD. DL2 is forced low in shutdown. DL2 is also forced high when an output overvoltage fault is detected. DL2 is forced low in skip mode after an inductor current zero crossing (GND2 - LX2) is detected. Supply Voltage Input for the DL_ Drivers. VDD is also the supply voltage used to internally recharge the BST_ flying capacitors during the off-time. Connect VDD to the 4.5V to 5.5V system supply voltage. Bypass VDD to GND with a 2.2F or greater ceramic capacitor. SMPS1 Low-Side Gate-Driver Output. DL1 swings from GND1 to VDD. DL1 is forced low in shutdown. DL1 is also forced high when an output overvoltage fault is detected. DL1 is forced low in skip mode after an inductor current zero crossing (GND1 - LX1) is detected. Boost Flying Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between VDD and BST1 charges the flying capacitor during the time the low-side FET is on. SMPS1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also used as an input to SMPS1's zero-crossing comparator. SMPS1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown. Active-Low Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below 1.5V (30% of VCC). VRHOT is high impedance in shutdown. Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC and GND) to THRM. Select the components so the voltage at THRM falls below 1.5V (30% of VCC) at the desired high temperature. Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with a 1F minimum capacitor. A VCC UVLO event that occurs while the IC is functioning is latched, and can only be cleared by cycling VCC power or by toggling SHDN.
24
DL2
25
VDD
26
DL1
27 28 29 30
BST1 LX1 DH1 VRHOT
31
THRM
32
VCC
18
______________________________________________________________________________________
AMD 2-/3-Output Mobile Serial VID Controller
Pin Description (continued)
PIN 33 NAME CSP1 FUNCTION Positive Current-Sense Input for SMPS1. Connect to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. Negative Current-Sense Input for SMPS1. Connect to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. A 20 discharge FET is enabled from CSN1 to PGND when the SMPS1 is shut down. Feedback Sense Input for SMPS1. Connect a resistor RFBDC1 between FBDC1 and the positive side of the feedback remote sense, and a capacitor from FBAC1 to couple the AC ripple from FBAC1 to FBDC1. An integrator on FBDC1 corrects for output ripple and ground-sense offset. 35 FBDC1 To enable a DC load-line less than the AC load-line, add a resistor from FBAC1 to FBDC1. To enable a DC load-line equal to the AC load-line, short FBAC1 to FBDC1. See the Core SteadyState Voltage Positioning (DC Droop) section. FBDC1 is high impedance in shutdown. Output of the AC Voltage-Positioning Transconductance Amplifier for SMPS1. The RC network between this pin and the positive side of the remote-sensed output voltage sets the transient AC droop:
MAX17480
34
CSN1
RDROOP _ AC1 =
36 FBAC1
RFBAC1 x RFBDC1 x RSENSE1 x Gm(FBAC1) RFBAC1 + RFBDC1 + RFB1 Z CFB1
where RDROOP_AC1 is the transient (AC) voltage-positioning slope that provides an acceptable trade-off between stability and load-transient response, Gm(FBAC1) = 2mS (typ), RSENSE1 is the value of the current-sense element that is used to provide the (CSP1, CSN1) current-sense voltage, ZCFB1 is the impedance of CFB1, and FBAC1 is high impedance in shutdown. SMPS1 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS1 internally connects to a transconductance amplifier that fine tunes the output voltage-- compensating for voltage drops from the SMPS ground to the load ground. Connect GNDS1 or GNDS2 above 0.9V combined-mode operation (unified core). When GNDS1 is pulled above 0.9V, GNDS2 is used as the remote ground-sense input. Four-Level Input to Enable Offset and Change Core SMPS Address OPTION VCC 3.3V 2V 38 OPTION GND OFFSET ENABLED 0 0 1 1 SMPS1 ADDRESS BIT 1 (VDD0) BIT 2 (VDD1) BIT 1 (VDD0) BIT 2 (VDD1) SMPS2 ADDRESS BIT 2 (VDD1) BIT 1 (VDD0) BIT 2 (VDD1) BIT 1 (VDD0)
37
GNDS1
When OFFSET is enabled, the MAX17480 enables a fixed +12.5mV offset on SMPS1 and SMPS2 VID codes after PGD_IN goes high. This configuration is intended for applications that implement a load line. An external resistor at FBDC_ sets the load-line. The offset can be disabled by setting the PSI_L bit to 0 through the serial interface. Additionally, the OPTION level also allows core SMPS1 and SMPS2 to take on either the VDD0 or VDD1 addresses. VDD0 refers to CORE0, and VDD1 refers to CORE1 for the AMD CPU. The NB SMPS is not affected by the OPTION setting.
______________________________________________________________________________________
19
AMD 2-/3-Output Mobile Serial VID Controller MAX17480
Pin Description (continued)
PIN NAME FUNCTION Oscillator Adjustment Input. Connect a resistor (ROSC) between OSC and GND to set the switching frequency (per phase): f OSC = 300kHz x 143k /R OSC 39 OSC A 71.4k to 432k resistor corresponds to switching frequencies of 600kHz to 100kHz, respectively, for SMPS1 and SMPS2. SMPS3 runs at twice the programmed switching frequency. Switching frequency selection is limited by the minimum on-time. See the Core Switching Frequency description in the SMPS Design Procedure section. Slew-Rate Adjustment Pin. The total resistance RTIME from TIME to GND sets the internal slew rate: PWM slew rate = (6.25mV/s) x (143k /RTIME) where RTIME is between 35.7k 40 TIME and 357k . This slew rate applies to both upward and downward VID transitions, and to the transition from boot mode to VID mode. Downward VID transition slew rate in skip mode can appear slower because the output transition is not forced by the SMPS. The slew rate for startup is fixed at 1mV/s. EP PGND Exposed Pad. Power ground connection and source connection of the internal low-side MOSFET.
20
______________________________________________________________________________________
AMD 2-/3-Output Mobile Serial VID Controller MAX17480
Table 1. Component Selection for Standard Applications
COMPONENT VIN = 7V TO 24V, V OUT1 = VOUT2 = 1.0V TO 1.3V, 18A PER PHASE Separate, 2-phase mobile (GNDS1 = GNDS2 = low) 300kHz (2) 10F, 25V Taiyo Yuden TMK432BJ106KM (2) 330F, 2V, 6m , low-ESR capacitor Panasonic EEFSX0D331XE SANYO 2TPE330M6 (1) Vishay/Siliconix SI7634DP (2) Vishay/Siliconix SI7336ADP 3A, 40V Schottky diode Central Semiconductor CMSH3-40 0.45H, 21A, 1.1m power inductor Panasonic ETQP4LR45WFC 600kHz (1) 10F, 6.3V TDK C2012X5R0J106M Taiyo Yuden JMK212BJ106M (1) 220F, 2V, 6m , low-ESR capacitor Panasonic EEFSD0D221R SANYO 2TPE220M6 None None VIN3 = 5V, V OUT3 = 1.0V TO 1.3V, 4A -- VIN = 4.5V TO 14V, V OUT1 = VOUT2 = 1.0V TO 1.3V, 18A PER PHASE Separate, 2-phase mobile (GNDS1 = GNDS2 = low) 500kHz (2) 10F, 16V Taiyo Yuden TMK432BJ106KM (2) 220F, 2V, 6m , low-ESR capacitor Panasonic EEFSD0D221R SANYO 2TPE220M6 (1) International Rectifier IRF7811W (2) Vishay/Siliconix SI7336ADP 3A, 40V Schottky diode Central Semiconductor CMSH3-40 0.36H, 21A, 1.1m power inductor Panasonic ETQP4LR36WFC 1MHz (1) 10F, 6.3V TDK C2012X5R0J106M Taiyo Yuden JMK212BJ106M (1) 47F, ceramic capacitor VIN3 = 3.3V, V OUT3 = 1.0V TO 1.3V, 4A --
Mode Switching Frequency CIN_ Input Capacitor
C OUT_ Output Capacitor NH_ High-Side MOSFET NL_ Low-Side MOSFET DL_ Schottky Rectifier (if needed)
None None
None 1.5H, 5A, 21m power inductor NEC/Tokin MPLCH0525LIR5 Toko FDV0530-1R5M
None
L_ Inductor
0.6H, 4.95A, 16m power inductor Sumida CDR6D23MN
Note: Mobile applications should be designed for separate mode operation. Component selection is dependent on AMD CPU AC and DC specifications.
Table 2. Component Suppliers
MANUFACTURER AVX Corporation BI Technologies Central Semiconductor Corp. Fairchild Semiconductor International Rectifier KEMET Corp. NEC TOKIN America, Inc. Panasonic Corp. WEBSITE www.avxcorp.com www.bitechnologies.com www.centralsemi.com www.fairchildsemi.com www.irf.com www.kemet.com www.nec-tokinamerica.com www.panasonic.com MANUFACTURER Pulse Engineering Renesas Technology Corp. SANYO Electric Co., Ltd. Siliconix (Vishay) Sumida Corp. Taiyo Yuden TDK Corp. TOKO America, Inc. WEBSITE www.pulseeng.com www.renesas.com www.sanyodevice.com www.vishay.com www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com
Standard Application Circuit
The MAX17480 standard application circuit (Figure 2) generates two independent 18A outputs and one 4A
output for AMD mobile CPU applications. See Table 1 for component selections. Table 2 lists the component manufacturers.
______________________________________________________________________________________
21
AMD 2-/3-Output Mobile Serial VID Controller MAX17480
RVCC 10 CVDD 1F 27 PWR CBST1 0.22F NH1 PWR 1 13 12 SERIAL INPUT 11 19 8 ILIM12 VDDIO SVC SVD PGD_IN SHDN CSN1 38 OPTION CSP2 18 CCS2 CSN2 2x 100k 20 30 RTHRM VCC RNTC ILIM3 VCC GND SMPS3 ILX3_PK (A) OFFSET (mV) 4-LEVEL VCC ILIM3 +12.5 5.25 +12.5 4.25 31 PWRGD VRHOT THRM DH2 21 BST2 23 CBST2 0.22F NH2 PWR LX2 DL2 2 ILIM3 RFBAC1 2k CFB1 2200pF RFBDC1 2k PWR L3 1.5H VOUT3/4A INTERNAL 4A NB REGULATOR COUT3 220F 6m PWR 0 NB SENSE_H 4700pF AGND 10 9 CBST3 0.1F 5, 6 GNDS1 LX3 37 100 4700pF AGND 15 RFBAC2 2k CFB2 2200pF RFBDC2 2k AGND EP = PGND PWR AGND AGND PWR GNDS2 14 100 4700pF 22 24 NL2 DL2 RLX2 CLX2 CDCR2 PWR CSP2 100 CORE0 SENSE_H 4700pF AGND CORE0 SENSE_L CSN2 L2 0.45H VOUT2/18ATDC COUT2 2x 330F 6m PWR CIN2 17 34 LX1 DL1 28 26 NL1 DL1 RLX1 CLX1 L1 0.45H VOUT1/18ATDC COUT1 2x 330F 6m PWR CDCR1 CSP1 33 CCS1 RCSP1 PWR CSP1 RCSN1 CSN1 CCSN1 AGND RCSP2 CSP2 RCSN2 CSN2 CCSN2 AGND VIN 4V TO 26V CORE1 18A REGULATOR CSP1 CSN1 CORE0 18A REGULATOR CIN1 +5V
CVCC 2.2F
32 ROSC 39 40 RILIM1 VCC OSC TIME
25 VDD BST1
VIN 4V TO 26V
DH1
29
AGND 1.5V OR 1.8V
RILIM2
RDCR1
MAX17480
SYSTEM POWER-GOOD ON OFF SMPS1 ADDR BIT1 (VDD0) BIT2 (VDD1) BIT1 (VDD0) BIT2 (VDD1) SMPS2 ADDR BIT2 (VDD1) BIT1 (VDD0) BIT2 (VDD1) BIT1 (VDD0) +3.3V
OPTION VCC 3.3V 2V GND
OFFSET 0 0 1 1
AGND
RDCR2
FBAC1 VIN_NB 2.7V TO 5.5V 3, 4 CIN_NB IN3 FBDC1
36
35
7
BST3 FBAC2 OUT3 FBDC2
16
100 CORE1 SENSE_H 4700pF AGND CORE1 SENSE_L ANALOG GROUND POWER GROUND
Figure 2. Griffin/Puma Standard Application Circuit
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
RVCC 10 CVDD 1F 27 PWR CBST1 0.22F NH1 PWR 1 13 12 SERIAL INPUT 11 19 8 ILIM12 VDDIO SVC SVD PGD_IN SHDN CSN1 38 OPTION CSP2 18 CCS2 CSN2 2x 100k 20 30 RTHRM VCC RNTC ILIM3 VCC GND ILX3_PK (A) 5.25 4.25 SMPS3 OFFSET (mV) 4-LEVEL VCC ILIM3 +12.50 +12.50 31 PWRGD VRHOT THRM DH2 21 BST2 23 CBST2 0.22F NH2 PWR LX2 DL2 2 ILIM3 RFBAC1 2k CFB1 2200pF RFBDC1 2k PWR L3 1.5H VOUT3/4A INTERNAL 4A NB REGULATOR COUT3 220F 6m PWR 100 NB SENSE_H 4700pF AGND 10 9 CBST3 0.1F 5, 6 GNDS1 LX3 37 100 4700pF AGND 15 RFBAC2 2k CFB2 2200pF RFBDC2 2k AGND EP = PGND PWR AGND PWR GNDS2 14 22 24 NL2 DL2 RLX2 CLX2 CDCR2 PWR CSP2 100 CORE0 SENSE_H 4700pF AGND CORE0 SENSE_L CSN2 L2 0.45H CIN2 17 34 LX1 DL1 28 26 NL1 DL1 RLX1 CLX1 L1 0.45H CIN1 +5V
CVCC 2.2F
32 ROSC 39 40 RILIM1 VCC OSC TIME
25 VDD BST1
VIN 4V TO 26V
DH1
29
AGND 1.5V OR 1.8V
RILIM2
RDCR1
MAX17480
CSP1 33 CCS1 RCSP1 PWR CSP1 RCSN1 CSN1 CCSN1 AGND RCSP2 CSP2 RCSN2 CSN2 CCSN2 AGND VIN 4.5V TO 28V CSP1
CDCR1 CSN1
SYSTEM POWER-GOOD ON OFF SMPS1 ADDR BIT1 (VDD0) BIT2 (VDD1) BIT1 (VDD0) BIT2 (VDD1) SMPS2 ADDR BIT2 (VDD1) BIT1 (VDD0) BIT2 (VDD1) BIT1 (VDD0) +3.3V
OPTION VCC OPEN REF GND
OFFSET 0 0 1 1
VCORE/36ATDC COUT 3x330F 6m PWR
36A CORE REGULATOR
AGND
RDCR2
FBAC1 VIN_NB 2.7V TO 5.5V 3, 4 CIN_NB IN3 FBDC1
36
35
7
BST3 FBAC2 OUT3 FBDC2
16
100 VCORE 4700pF AGND VDDIO ANALOG GROUND POWER GROUND
CONNECT GNDS2 TO VDDIO FOR UNIFIED CORE OPERATION
Figure 3. Caspian/Tigris Standard Application Circuit
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
0.3 x VCC SHDN FAULT1 FAULT2 FAULT3 VCC REF (2.0V) AGND OFS_EN 7-BIT VID ADDR SVI INTERFACE PGD_IN VDDIO SVC SVD TIME GNDS2 GNDS MUX GNDS1 COMBINE DETECT SKIP1 DAC1 DACOUT1 REFOK SMPS1 TARGET AND SLEW RATE BLOCK VDDIO x2 UVLO RUN BST_ PWM_ BLANK1 TARGET1 GNDS1 PWR BLANK2 7-BIT VID SKIP2 DAC2 DACOUT2 SMPS2 TARGET AND SLEW RATE BLOCK TARGET2 GNDS2 BLANK3 SMPS3 TARGET AND SLEW RATE BLOCK TARGET3 PWM_ CSA_ TARGET_ IMAX_ IMIN_ SKIP_ CLOCK_ ISLOPE_ COMBINE COMBINE x2 IMAX_ IMIN_ ILIM12 CURRENT LIMIT CSA_ REF SKIP_ FBDC1 TARGET1 BLANK1 FBDC2 OPTION 4-LEVEL DECODE OFS_EN ADDR CLOCK1 CLOCK2 CLOCK3 ISLOPE1 ISLOPE2 ISLOPE3 TARGET2 BLANK2 OUT3 TARGET3 BLANK3 SMPS3 FAULT BLOCK SMPS2 FAULT BLOCK SMPS1 FAULT BLOCK FAULT1 PGD1 TARGET3 SKIP3 CSN3 PGD2 FAULT2 SMPS3 DRIVER BLOCK PWR PGD3 FAULT3 ILIM3 PWRGD PGND LX3 CSP3 SMPS1 AND SMPS2 PWM BLOCK FBAC_ FBDC_ CSN_ CSP_ x2 SKIP_ SMPS1 AND SMPS2 DRIVER BLOCK DH_ LX_ DL_ PGND VRHOT
MAX17480
THRM VDD
7-BIT VID SKIP3
DAC3
DACOUT3
OUT3 BST3 IN3
OSC
OSCILLATOR
Figure 4. Functional Diagram
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AMD 2-/3-Output Mobile Serial VID Controller
Detailed Description
The MAX17480 consists of a dual fixed-frequency PWM controller with external switches that generate the supply voltage for two independent CPU cores and one low-input-voltage internal switch SMPS for the separate NB SMPS. The CPU core SMPSs can be configured as independent outputs, or as a combined output by connecting the GNDS1 or GNDS2 pin-strap high (GNDS1 or GNDS2 pulled to 1.5V to 1.8V, which are the respective voltages for DDR3 and DDR2). All three SMPSs can be programmed independently to any voltage in the VID table (see Table 4) using the serial VID interface (SVI). The CPU is the SVI bus master, while the MAX17480 is the SVI slave. Voltage transitions are commanded by the CPU as a single step command from one VID code to another. The MAX17480 slews the SMPS outputs at the slew rate programmed by the external RTIME resistor during VID transitions and the transition from boot mode to VID mode. During startup, the MAX17480 SMPSs are always in pulse-skipping mode. After exiting the boot mode, the individual PSI_L bit sets the respective SMPS into pulse-skipping mode or forced-PWM mode, depending on the system power state, and adds the +12.5mV offset for core supplies if enabled by the OPTION pin. In combined mode, the PSI_L bit adds the +12.5mV offset if enabled by the OPTION pin, and switches from 1-phase pulse-skipping mode to 2-phase PWM mode. Figure 4 is the MAX17480 functional diagram. gate charge of the external MOSFETs as defined in the MOSFET data sheets, and Q G_NB is approximately 2nC. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup.
MAX17480
Switching Frequency (OSC)
Connect a resistor (ROSC) between OSC and GND to set the switching frequency (per phase): fSW = 300kHz x 143k/ROSC A 71.4k to 432k resistor corresponds to switching frequencies of 600kHz to 100kHz, respectively, for the core SMPSs, and 1.2MHz to 200kHz for the NB SMPS. Highfrequency (600kHz) operation for the core SMPS optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This might be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low-frequency (100kHz) operation offers the best overall efficiency at the expense of component size and board space. The NB SMPS runs at twice the switching frequency of the core SMPSs. The low power of the NB rail allows for higher switching frequencies with little impact on the overall efficiency. Minimum on-time (tON(MIN)) must be taken into consideration when selecting a switching frequency. See the Core Switching Frequency description in the SMPS Design Procedure section.
+5V Bias Supply (VCC, VDD) The MAX17480 requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook's main 95%-efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear SMPS that would otherwise be needed to supply the PWM circuit and gate drivers.
The 5V bias supply powers both the PWM controller and internal gate-drive power, so the maximum current drawn is: IBIAS = ICC + fSW_COREQG_CORE + fSW_NBQG_NB = 50mA to 70mA (typ) where ICC is provided in the Electrical Characteristics table, fSW_CORE and fSW_NB are the respective core and NB SMPS switching frequencies, QG_CORE is the
Interleaved Multiphase Operation
The MAX17480 interleaves both core SMPSs' phases-- resulting in 180 out-of-phase operation that minimizes the input and output filtering requirements, reduces electromagnetic interference (EMI), and improves efficiency. The high-side MOSFETs do not turn on simultaneously during normal operation. The instantaneous input current is effectively reduced by the number of active phases, resulting in reduced input-voltage ripple, effective series resistance (ESR) power loss, and RMS ripple current (see the Core Input Capacitor Selection section). Therefore, the controller achieves high performance while minimizing the component count--which reduces cost, saves board space, and lowers component power requirements--making the MAX17480 ideal for high-power, cost-sensitive applications.
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AMD 2-/3-Output Mobile Serial VID Controller
Transient Phase Repeat When a transient occurs, the output voltage deviation depends on the controller's ability to quickly detect the transient and slew the inductor current. A fixed-frequency controller typically responds only when a clock edge occurs, resulting in a delayed transient response. To minimize this delay time, the MAX17480 includes enhanced transient detection and transient phase repeat capabilities. If the controller detects that the output voltage has dropped by 41mV, the transient detection comparator immediately retriggers the phase that completed its on-time last. The controller triggers the subsequent phases as normal, on the appropriate oscillator edges. This effectively triggers a phase a full cycle early, increasing the total inductor-current slew rate and providing an immediate transient response.
MAX17480
IFBAC = Gm(FBAC) VCS where VCS = VCSP - VCSN is the differential current-sense voltage, and Gm(FBAC) is typically 2mS as defined in the Electrical Characteristics table. DC droop is typically used together with the +12.5mV offset feature to keep within the DC tolerance window of the application. See the Offset and Address Change for Core SMPSs (OPTION) section. The ripple voltage on FBDC must be less than the -33mV (max) transient phase repeat threshold:
RFBAC I LRSENSEGm(FBAC)RFBDC + I LRESR RFBAC + RFBDC + RFB 33mV 2
RFBDC
(66mV - I LRESR ) (RFBAC + RFB )
RFBAC I LRSENSEGm(FBAC) - 66mV
Core SMPS Feedback Adjustment Amplifiers
The MAX17480 provides an FBAC and FBDC pin for each SMPS to allow for flexible AC and DC droop settings. FBAC is the output of an internal transconductance amplifier that outputs a current proportional to the current-sense signal. FBDC is the feedback input that is compared against the internal target. Place resistors and capacitors at the FBAC and FBDC pins as shown in Figure 5. With this configuration, the DC droop is always less than or equal to the AC droop.
where IL is the inductor ripple current, RESR is the effective output ESR at the remote sense point, RSENSE is the current-sense element, and Gm(FBAC) is 2.06mS (max) as defined in the Electrical Characteristics table. The worst-case inductor ripple occurs at the maximum input-voltage and maximum output-voltage conditions: VOUT(MAX) VIN(MAX) - VOUT(MAX) I L(MAX) = VIN(MAX) fSW L
(
)
To make the DC and AC load-lines the same, directly short FBAC to FBDC. To disable DC voltage positioning, remove RFB, which connects FBAC to FBDC.
MAX17480
CSP CSN CFB ERROR AMP FBDC RFB RFBDC 100 CORE SENSE_H 4700pF TARGET Gm(FBAC) FBAC RFBAC
AGND
Figure 5. Core SMPS Feedback Connection
Core Steady-State Voltage Positioning (DC Droop) FBDC is the feedback input to the error amplifier. Based on the configuration in Figure 5, the core SMPS output voltage is given by:
VOUT = VTARGET - RFBDC x RFBAC x IFBAC RFBAC + RFBDC + RFB
Core Transient Voltage-Positioning Amplifier (AC Droop) Each of the MAX17480 core supply SMPSs includes one transconductance amplifier for voltage positioning. The amplifiers' inputs are generated by summing their respective current-sense inputs, which differentially sense the voltage across either current-sense resistor or the inductor's DCR. The voltage-positioning droop amplifier's output (FBAC) connects to the remote-sense point of the output through an RC network that sets each phase's AC voltage-positioning gain:
VOUT = VTARGET - RFBAC x R FBDC RFBAC + R FBDC + R FB ZCFB I FBDC
where the target voltage (VTARGET) is defined in the Nominal Output-Voltage Selection section, and the FBAC amplifier's output current (IFBAC) is determined by each phase's current-sense voltage:
26
where the target voltage (VTARGET) is defined in the Nominal Output-Voltage Selection section, ZCFB is the effective impedance of CFB, and the FBAC amplifier's output current (IFBAC) is determined by each phase's current-sense voltage:
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AMD 2-/3-Output Mobile Serial VID Controller
I FBAC = Gm(FBAC) VCS where VCS = VCSP - VCSN is the differential currentsense voltage, and G m(FBAC) is 2.06mS (max) as defined in the Electrical Characteristics table. AC droop is required for stable operation of the MAX17480. A minimum of 1.5mV/A is recommended. AC droop must not be disabled.
Core Differential Remote Sense The MAX17480 controller includes independent differential, remote-sense inputs for each CPU core to eliminate the effects of voltage drops along the PCB traces and through the processor's power pins. The feedback-sense (FBDC_) input connects to the remote-sensed output through the resistance at FBDC_ (RFBDC_). The groundsense (GNDS_) input connects to an amplifier that adds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. Connect the feedback-sense (FBDC_) RFBDC_ resistor and ground-sense (GNDS_) input directly to the respective CPU core's remotesense outputs as shown in Figure 2. GNDS1 and GNDS2 are dual-function pins. At power-on, the voltage levels on GNDS1 and GNDS2 configure the MAX17480 as two independent switching SMPSs, or one higher current 2-phase SMPS. Keep both GNDS1 and GNDS2 low during power-up to configure the MAX17480 in separate mode. Connect GNDS1 or GNDS2 to a voltage above 0.8V (typ) for combined-mode operation. In the AMD mobile system, this is automatically done by the CPU that is plugged into the socket that pulls GNDS1 or GNDS2 the VDDIO voltage level. When GNDS1 is pulled high to indicate combinedmode operation, the remote ground sense is automatically switched to GNDS2. When GNDS2 is pulled high to indicate combined-mode operation, the remote ground sense is automatically switched to GNDS1. GNDS1 and GNDS2 do not dynamically switch in the real application. It is only switched when one CPU is removed (e.g., split-core CPU), and another is plugged in (e.g., combined-core CPU). This should not be done when the socket is "hot" (i.e., powered). The MAX17480 checks the GNDS1 and GNDS2 levels at the time when the internal REFOK signal goes high, and latches the operating mode information (separate or combined mode). This latch is cleared by cycling the SHDN pin.
Core Integrator Amplifier An internal integrator amplifier forces the DC average of the FBDC_ voltage to equal the target voltage. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 4), allowing accurate DC output-voltage regulation regardless of the output ripple voltage. The MAX17480 disables the integrator during downward VID transitions done in pulse-skipping mode. The integrator remains disabled until the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). The integrator amplifier can shift the output voltage by 80mV (min). The maximum difference between transient AC droop and DC droop should not exceed 80mV at the maximum allowed load current to guarantee proper DC output-voltage accuracy over the full load conditions.
MAX17480
NB SMPS Feedback Adjustment Amplifiers
NB Steady-State Voltage Positioning (DC Droop) The NB SMPS has a built-in load-line that is -5.5mV/A. The output peak voltage (VOUT3_PK+) is set to:
VOUT3_PK = VTARGET3 - 5.5mV/A x (I LOAD3 + L 3 ) 2 ( V - VOUT3 ) x VOUT3 I L3 = IN3 L3 x VIN3 x fSW 3 where the target voltage (VTARGET3) is defined in the Nominal Output-Voltage Selection section, fSW3 is the NB switching frequency, and ILOAD3 is the output load current of the NB SMPS.
I
2-Wire Serial Interface (SVC, SVD)
The MAX17480 supports the 2-wire, write-only, serialinterface bus as defined by the AMD serial VID interface specification. The serial interface is similar to the high-speed 3.4MHz I2C bus, but without the master mode sequence. The bus consists of a clock line (SVC) and a data line (SVD). The CPU is the bus master, and the MAX17480 is the slave. The MAX17480 serial interface works from 100kHz to 3.4MHz. In the AMD mobile application, the bus runs at 3.4MHz. The serial interface is active only after PGD_IN goes high in the startup sequence. The CPU sets the VID voltage of the three internal DACs and the PSI_L bit through the serial interface. During the startup sequence, the SVC and SVD inputs serve an alternate function to set the 2-bit boot VID for all three DACs while PWRGD is low.
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
Nominal Output-Voltage Selection
Core SMPS Output Voltage The nominal no-load output voltage (VTARGET) for each SMPS is defined by the selected voltage reference (VID DAC) plus the remote ground-sense adjustment (VGNDS) and the offset voltage (VOFFSET) as defined in the following equation:
VTARGET = VFBDC = VDAC + VGNDS + VOFFSET where VDAC is the selected VID voltage of the core SMPS DAC, VGNDS is the ground-sense correction voltage for core supplies, and VOFFSET is the +12.5mV offset enabled by the OPTION pin when the PSI_L is set high for core supplies.
Table 3. Boot Voltage Code Table
SVC
0 0 1 1
SVD
0 1 0 1
BOOT VOLTAGE V OUT (V)
1.1 1.0 0.9 0.8
NB SMPS Output Voltage The nominal output voltage (VTARGET) for the NB is defined by the selected voltage reference (VID DAC) plus the offset voltage (VOFFSET_NB) as defined in the following equation:
VTARGET3 = VOUT3 = VDAC + VOFFSET _ NB where VDAC is the selected VID voltage of the NB DAC, and VOFFSET_NB is +12.5mV.
Core SMPS Offset A +12.5mV offset can be added to both core SMPS DAC voltages for applications that include DC droop. The offset is applied only after the MAX17480 exits boot mode (PGD_IN going from low to high), and the MAX17480 enters the serial-interface mode. The offset is disabled when the PSI_L bit is set, saving more power when the load is light. The OPTION pin setting enables or disables the +12.5mV offset. Connect OPTION to OSC (2V) or GND to enable the offset. Keep OPTION connected to 3.3V or V CC to disable the offset. See the Offset and Address Change for Core SMPSs (OPTION) section. NB SMPS Offset The NB SMPS output has a -5.5mV/A load line. A +12.5mV offset is added to keep the output within regulation over the full load. See the Offset and CurrentLimit Setting for NB SMPS (ILIM3) section.
7-Bit DAC Inside the MAX17480 are three 7-bit digital-to-analog converters (DACs). Each DAC can be individually programmed to different voltage levels by the serial-interface bus. The DAC sets the target for the output voltage for the core and NB SMPSs. The available DAC codes and resulting output voltages are compatible with the AMD SVI (Table 4) specifications. Boot Voltage On startup, the MAX17480 slews the target for all three DACs from ground to the boot voltage set by the SVC and SVD pin-voltage levels. While the output is still below regulation, the SVC and SVD levels can be changed, and the MAX17480 sets the DACs to the new boot voltage. Once the programmed boot voltage is reached and PWRGD goes high, the MAX17480 stores the boot VID. Changes in the SVC and SVD settings do not change the output voltage once the boot VID is stored. When PGD_IN goes high, the MAX17480 exits boot mode, and the three DACs can be independently set to any voltage in the VID table by the serial interface. If PGD_IN goes from high to low any time after the boot VID is stored, the MAX17480 sets all three DACs back to the voltage of the stored boot VID. Table 3 is the boot voltage code table.
Output-Voltage Transition Timing
SMPS Output-Voltage Transition The MAX17480 performs positive voltage transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-intime arrival at the new output-voltage level with the lowest possible peak currents for a given output capacitance. The slew rate (set by resistor RTIME) must be set fast enough to ensure that the transition is completed within the maximum allotted time for proper CPU operation. RTIME is between 35.7k and 357k for corresponding slew rates between 25mV/s to 2.5mV/s, respectively, for the SMPSs. At the beginning of an output-voltage transition, the MAX17480 blanks both PWRGD comparator thresholds, preventing the PWRGD open-drain output from changing states during the transition. At the end of an upward VID transition, the controller enables both PWRGD thresholds approximately 20s after the slew-rate controller reaches the target output voltage. At the end
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
SVC/SVD BUS IDLE BUS IDLE BUS IDLE
SMPS LOAD PWRGD UPPER THRESHOLD SMPS VOLTAGE (SMPS TARGET) PWRGD LOWER THRESHOLD PWRGD BLANK HIGH-Z 20s
LIGHT LOAD UPPER THRESHOLD BLANKED SMPS TARGET
HEAVY LOAD
BLANK HIGH-Z 20s
BLANK HIGH-Z 20s
Figure 6. VID Transition Timing
of a downward VID transition, the upper PWRGD threshold is enabled only after the output reaches the lower VID code setting. Figure 6 shows VID transition timing. The MAX17480 automatically controls the current to the minimum level required to complete the transition in the calculated time. The slew-rate controller uses an internal capacitor and current source programmed by RTIME to transition the output voltage. The total transition time depends on RTIME, the voltage difference, and the accuracy of the slew-rate controller (C SLEW accuracy). The slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit set by ILIM12 for the core SMPSs and ILIM3 for the NB SMPS. For all dynamic positive VID transitions or negative VID transitions in forcedPWM mode (PSI_L set to 1), the transition time (tTRAN) is given by: - VOLD V t TRAN = NEW ( dVTARGET /dt )
If the SMPS is in a pulse-skipping mode (PSI_L set to 0), the discharge rate of the output voltage during downward transitions is then dependent on the load current and total output capacitance for loads less than a minimum current, and dependent on the RTIME programmed slew rate for heavier loads. The critical load current (ILOAD(CRIT)) where the transition time is dependent on the load is: ILOAD(CRIT) COUT x ( dVTARGET /dt ) For load currents less than ILOAD(CRIT), the transition time is: C x dVTARGET t TRAN OUT ILOAD For soft-start, the controller uses a fixed slew rate of 1mV/s. In shutdown, the outputs are discharged using a 20 switch through the CSN_ pins for the core SMPSs and through the OUT3 pin for the NB SMPS.
where dVTARGET/dt = 6.25mV/s x 143k/RTIME is the slew rate, VOLD is the original output voltage, and VNEW is the new target voltage. See the Slew-Rate Accuracy in the Electrical Characteristics table for slew-rate limits. The output voltage tracks the slewed target voltage, making the transitions relatively smooth. The average inductor current per phase required to make an output voltage transition is: IL COUT x ( dVTARGET /dt
Forced-PWM Operation
After exiting the boot mode and if the PSI_L bit is set to 1, the MAX17480 operates with the low-noise, forcedPWM control scheme. Forced-PWM operation disables the zero-crossing comparator, forcing the low-side gate-drive waveforms to constantly be the complement of the high-side gate-drive waveforms. This keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative output-voltage transitions by quickly discharging the output capacitors. Forced-PWM operation comes at a cost: the no-load +5V bias supply current remains between 50mA to 70mA,
29
)
where dVTARGET/dt is the required slew rate and COUT is the total output capacitance of each phase.
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
depending on the external MOSFETs and switching frequency. To maintain high efficiency under light load conditions, the processor could switch the controller to a low-power pulse-skipping control scheme. current, the controller must skip pulses to avoid overcharging the output. When the clock edge occurs, if the output voltage still exceeds the feedback threshold, the controller does not initiate another on-time. This forces the controller to actually regulate the valley of the output voltage ripple under light load conditions.
Pulse-Skipping Operation
During soft-start and in power-saving mode--when the PSI_L bit is set to 0--the MAX17480 operates in pulseskipping mode. Pulse-skipping mode enables the driver's zero-crossing comparator, so the driver pulls its DL low when "zero" inductor current is detected (VGND - VLX = 0). This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light load conditions to avoid overcharging the output. In pulse-skipping operation, the controller terminates the on-time when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the idle-mode current-sense threshold (VIDLE = 0.15 x VLIMIT for the core SMPS and ILX3MIN = 0.25 x ILX3PK setting for the NB SMPS). Under heavy load conditions, the continuous inductor current remains above the idle-mode current-sense threshold, so the on-time depends only on the feedback voltage threshold. Under light load conditions, the controller remains above the feedback voltage threshold, so the on-time duration depends solely on the idle-mode currentsense threshold, which is approximately 15% of the fullload peak current-limit threshold set by ILIM12 for the core SMPSs and 25% of the full-load peak current-limit threshold set by ILIM3 for the NB SMPS. During downward VID transitions, the controller temporarily sets the OVP threshold of the SMPSs to 1.85V (typ), preventing false OVP faults. Once the error amplifier detects that the output voltage is in regulation, the OVP threshold tracks the selected VID DAC code. Each SMPS can be individually set to operate in pulseskipping mode when its PSI_L bit is set to 0, or set to operate in forced-PWM mode when its PSI_L bit is set to 1. When the core SMPSs are configured for combinedmode operation, core supplies operate in 1-phase pulse-skipping mode when PSI_L = 0, and core supplies are in 2-phase forced-PWM mode when PSI_L = 1.
Automatic Pulse-Skipping Crossover In skip mode, the MAX17480 zero-crossing comparators are active. Therefore, an inherent automatic switchover to PFM takes place at light loads, resulting in a highly efficient operating mode. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The driver's zero-crossing comparator senses the inductor current across the low-side MOSFET. Once VGND - VLX drops below the zero-crossing threshold, the driver forces DL low. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). The load-current level at which the PFM/PWM crossover occurs, ILOAD(SKIP), is given by:
V (V - V ) I LOAD(SKIP) = OUT IN OUT 2VINfSWL The switching waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-off in PFM noise vs. light-load efficiency is made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels).
Current Sense
Core SMPS Current Sense The output current of each phase is sensed differentially. A low offset voltage and high-gain differential current amplifier at each phase allows low-resistance currentsense resistors to be used to minimize power dissipation. Sensing the current at the output of each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, and the flexibility of using either a current-sense resistor or the DC resistance of the output inductor.
Idle-Mode Current-Sense Threshold The idle-mode current-sense threshold forces a lightly loaded SMPS to source a minimum amount of power with each on-time since the controller cannot terminate the on-time until the current-sense voltage exceeds the idle-mode current-sense threshold (V IDLE = 0.15 x VLIMIT for the core SMPS and ILX3MIN = 0.25 x ILX3PK setting for the NB SMPS). Since the zero-crossing comparator prevents the switching SMPS from sinking
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
Table 4. Output-Voltage VID DAC Codes
SVID[6:0] 000_0000 000_0001 000_0010 000_0011 000_0100 000_0101 000_0110 000_0111 000_1000 000_1001 000_1010 000_1011 000_1100 000_1101 000_1110 000_1111 001_0000 001_0001 001_0010 001_0011 001_0100 001_0101 001_0110 001_0111 001_1000 001_1001 001_1010 001_1011 001_1100 001_1101 001_1110 001_1111 OUTPUT VOLTAGE (V) 1.5500 1.5375 1.5250 1.5125 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 SVID[6:0] 010_0000 010_0001 010_0010 010_0011 010_0100 010_0101 010_0110 010_0111 010_1000 010_1001 010_1010 010_1011 010_1100 010_1101 010_1110 010_1111 011_0000 011_0001 011_0010 011_0011 011_0100 011_0101 011_0110 011_0111 011_1000 011_1001 011_1010 011_1011 011_1100 011_1101 011_1110 011_1111 OUTPUT VOLTAGE (V) 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 SVID[6:0] 100_0000 100_0001 100_0010 100_0011 100_0100 100_0101 100_0110 100_0111 100_1000 100_1001 100_1010 100_1011 100_1100 100_1101 100_1110 100_1111 101_0000 101_0001 101_0010 101_0011 101_0100 101_0101 101_0110 101_0111 101_1000 101_1001 101_1010 101_1011 101_1100 101_1101 101_1110 101_1111 OUTPUT VOLTAGE (V) 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 SVID[6:0] 110_0000 110_0001 110_0010 110_0011 110_0100 110_0101 110_0110 110_0111 110_1000 110_1001 110_1010 110_1011 110_1100 110_1101 110_1110 110_1111 111_0000 111_0001 111_0010 111_0011 111_0100 111_0101 111_0110 111_0111 111_1000 111_1001 111_1010 111_1011 111_1100 111_1101 111_1110 111_1111 OUTPUT VOLTAGE (V) 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 OFF OFF OFF OFF
Note: The NB SMPS output voltage has an offset of +12.5mV.
When using a current-sense resistor for accurate outputvoltage positioning, the circuit requires a differential RC filter to eliminate the AC voltage step caused by the equivalent series inductance (LESL) of the current-sense resistor (see Figure 7). The ESL-induced voltage step does not affect the average current-sense voltage, but
results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and early current-limit detection. Similar to the inductor DCR sensing method above, the RC filter's time constant should match the L/R time constant formed by the current-sense resistor's parasitic inductance:
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
INPUT (VIN) CIN DH_ LX_ COUT DL_ NL DL REQ CEQ NH L SENSE RESISTOR LESL RSENSE CEQREQ = LESL RSENSE
MAX17480
CSP_ CSN_ A) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) CIN DH_ LX_ COUT DL_ NL DL RLX CLX R1 R2 CEQ FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR. RDCR = L 1 1 x + CEQ R1 R2 NH INDUCTOR L RDCR RCS = R2 x RDCR R1 + R2
MAX17480
CSP_ CSN_ B) LOSSLESS INDUCTOR DCR SENSING
Figure 7. Current-Sense Configurations
LESL = REQCSENSE RSENSE where LESL is the equivalent series inductance of the current-sense resistor, RSENSE is current-sense resistance value, and CSENSE and REQ are the time-constant matching components. Using the DC resistance (RDCR) of the output inductor allows higher efficiency. In this configuration, the initial tolerance and temperature coefficient of the inductor's DCR must be accounted for in the output-voltage droop-error budget and power monitor. This currentsense method uses an RC filtering network to extract the current information from the output inductor (see Figure 7). The time constant of the RC network should match the inductor's time constant (L/RDCR): L = REQCSENSE RDCR where CSENSE and REQ are the time-constant matching components. To minimize the current-sense error due to
32
the current-sense inputs' bias current (ICSP and ICSN), choose REQ less than 2k and use the above equation to determine the sense capacitance (CSENSE). Choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is recommended for this current-sense method. See the Core Voltage Positioning and Loop Compensation section for detailed information. Additional RLX and CLX are always added between the LX_ and CSP_ pins if DCR sensing is used, and they provide additional overdrive to the current-sense signal to improve the noise immunity; otherwise, there might be too much jitter or the system could be unstable.
NB SMPS Current Sense The NB current sense is achieved by sensing the voltage across the high-side internal MOSFET during the on-time. The current information is computed by dividing the sensed voltage by the MOSFET's on-resistance, RON(NH3).
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AMD 2-/3-Output Mobile Serial VID Controller
Combined-Mode Current Balance When the core SMPSs are configured in combined mode (GNDS1 or GNDS2 pulled to V DDIO ), the MAX17480 current-mode architecture automatically forces the individual phases to remain current balanced. SMPS1 is the main voltage-control loop, and SMPS2 maintains the current balance between the phases. This control scheme regulates the peak inductor current of each phase, forcing them to remain properly balanced. Therefore, the average inductor current variation depends mainly on the variation in the currentsense element and inductance value. Peak Current Limit The MAX17480 current-limit circuit employs a fast peak inductor current-sensing algorithm. Once the currentsense signal of the SMPS exceeds the peak current-limit threshold, the PWM controller terminates the on-time. See the Core Peak Inductor Current Limit (ILIM12) section in the Core SMPS Design Procedure section.
Power-Up Sequence (POR, UVLO, PGD_IN)
Power-on reset (POR) occurs when VCC rises above approximately 3V, resetting the fault latch and preparing the controller for operation. The VCC undervoltage-lockout (UVLO) circuitry inhibits switching until VCC rises above 4.25V (typ). The controller powers up the reference once the system enables the controller VCC above 4.25V and SHDN is driven high. With the reference in regulation, the controller ramps the SMPS and NB voltages to the boot voltage set by the SVC and SVD inputs: tSTART = VBOOT (1mV/s )
MAX17480
The soft-start circuitry does not use a variable current limit, so full output current is available immediately. PWRGD becomes high impedance approximately 20s after the SMPS outputs reach regulation. The boot VID is stored the first time PWRGD goes high. The MAX17480 is in pulse-skipping mode during soft-start. Figure 8 shows the MAX17480 startup sequence.
1 DC_IN VDDIO
2
3
4
5
6
SVC/SVD
2-BIT BOOT VID
SERIAL MODE
BUS IDLE
SHDN GNDS1 OR GNDS2 (VDD_PLANE_STRAP) SMPS VOUT 7
PWRGD
20s 10s
BLANK HIGH-Z 20s
PGD_IN
RESET_L 8
Figure 8. Startup Sequence
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AMD 2-/3-Output Mobile Serial VID Controller
For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCC power supply below 0.5V. If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions and could also result in the stored boot VIDs being corrupted. As such, the MAX17480 immediately stops switching (DH_ and DL_ pulled low), latches off, and discharges the outputs using the internal 20 switches from CSN_ to GND. Notes for Figure 8: 1) The relationship between DC_IN and VDDIO is not guaranteed. It is possible to have VDDIO powered when DC_IN is not powered, and it is possible to have DC_IN power up before VDDIO powers up. 2) As the VDDIO power rail comes within specification, VDD_Plane_Strap becomes valid and SVC and SVD are driven to the boot VID value by the processor. The system guarantees that VDDIO is in specification and SVC and SVD are driven to the boot VID value for at least 10s prior to SHDN being asserted to the MAX17480. 3) After SHDN is asserted, the MAX17480 samples and latches the VDD_Plane_Strap level at its GNDS1 and GNDS2 pins when REF reaches the REFOK threshold, and ramps up the voltage plane outputs to the level indicated by the 2-bit boot VID. The boot VID is stored in the MAX17480 for use when PGD_IN deasserts. The MAX17480 soft-starts the output rails to limit inrush current from the DC_IN rail. The MAX17480 operates in pulse-skipping mode in the boot mode regardless of PSI_L settings. 4) The MAX17480 asserts PWRGD. After PWRGD is asserted and all system-wide voltage planes and free-running clocks are within specification, then the system asserts PGD_IN. 5) The processor holds the 2-bit boot VID for at least 10s after PGD_IN is asserted.
MAX17480
6) The processor issues the set VID command through SVI. 7) The MAX17480 transitions the voltage planes to the set VID. The set VID can be greater than or less than the boot VID voltage. The MAX17480 operates in pulse-skipping mode or forced-PWM mode according to the PSI_L setting. 8) The chipset enforces a 1ms delay between PGD_IN assertion and RESET_L deassertion.
PWRGD The MAX17480 features internal power-good fault comparators for each SMPS. The outputs of these individual power-good fault comparators are logically ORed to drive the gate of the open-drain PWRGD output transistor. Each SMPS's power-good fault comparator has an upper threshold of +200mV (typ) and a lower threshold of -300mV (typ). PWRGD goes low if the output of either SMPS exceeds its respective threshold. PWRGD is forced low during the startup sequence up to 20s after the output is in regulation. The 2-bit boot VID is stored when PWRGD goes high during the startup sequence. PWRGD is immediately forced low when SHDN goes low.
PWRGD is blanked high impedance while any of the internal SMPS DACs are slewing during a VID transition, plus an additional 20s after the DAC transition is completed. For downward VID transitions, the upper threshold of the particular power-good fault comparators remains blanked until the output reaches regulation again. PWRGD is blanked high impedance for each SMPS whose internal DAC is in off mode, and is pulled low if all three SMPS DACs are in off mode.
PGD_IN After the SMPS outputs reach the boot voltage, the MAX17480 switches to the serial-interface mode when PGD_IN goes high. Anytime during normal operation, a high-to-low transition on PGD_IN causes the MAX17480 to slew all three internal DACs back to the stored boot VIDs. The SVC and SVD inputs are disabled during the time that PGD_IN is low. The serial interface is reenabled when PGD_IN goes high again. Figure 9 shows PGD_IN timing.
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
PSI_L
PULSE-SKIPPING MODE
SVC/SVD SMPS VOUT (HIGH DAC TARGET)
BUS IDLE
2-BIT BOOT VID, SVC/SVD INPUTS DISABLED
BUS IDLE
TARGET
VOUT
(LOW DAC TARGET) SMPS VOUT PGD_IN
PWRGD
BLANK HIGH-Z 20s
BLANK HIGH-Z 20s
Figure 9. PGD_IN Timing
RPTC1 VCC RTHRM PLACE RNTC NEXT TO THE HOTTEST POWER COMPONENT. RNTC GND THRM VCC
MAX17480
PLACE RPTC1, RPTC2, AND RPTC3 NEXT TO THE RESPECTIVE SMPS'S POWER COMPONENT.
RPTC2 RPTC3 THRM RTHRM GND
MAX17480
Figure 10. THRM Configuration
Shutdown
When SHDN goes low, the MAX17480 enters shutdown mode. PWRGD is pulled low immediately and forces all DH and DL low, and all three outputs are discharged through the 20 internal discharge FETs through the CSN pin for core SMPSs and through the OUT3 pin for NB SMPSs.
VRHOT Temperature Comparator
The MAX17480 features an independent comparator with an accurate threshold (VHOT) that tracks the analog supply voltage (VHOT = 0.3VCC). Use a resistor- and thermistor-divider between V CC and GND to generate a
voltage-SMPS overtemperature monitor. Place the thermistor as close as possible to the MOSFETs and inductors. Place three individual thermistors near to each SMPS to monitor the temperature of the respective SMPS. When core SMPSs are in combined-mode operation, the current-balance circuit balances the currents between core SMPS phases. As such, the power loss and heat in each phase should be identical, apart from the effects of placement and airflow over each phase. Single thermistors can be placed near either of the phases and still be effective for core SMPS temperature monitoring, and one thermistor can be saved. See Figure 10.
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
Fault Protection (Latched)
Output Overvoltage Protection (OVP) The overvoltage protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX17480 continuously monitors the output for an overvoltage fault. The controller detects an OVP fault if the output voltage exceeds the set VID DAC voltage by more than 300mV. The OVP threshold tracks the VID DAC voltage except during a downward VID transition. During a downward VID transition, the OVP threshold is set at 1.85V (typ) until the output reaches regulation, when the OVP threshold is reset back to 300mV above the VID setting. When the OVP circuit detects an overvoltage fault in core SMPSs, it immediately sets the fault latch and forces the external low-side driver high on the faulted SMPS. The nonfaulted SMPSs are also shut down by turning on the internal passive discharge MOSFET. The synchronous-rectifier MOSFETs of the faulted side are turned on with 100% duty, which rapidly discharges the output filter capacitor and forces the output low. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. When the core SMPSs are configured in combined mode, the synchronous-rectifier MOSFETs of both phases are turned on with 100% duty in response to an overvoltage fault. Passive shutdown is initiated for the NB SMPS. The NB SMPS has no OVP. Output Undervoltage Protection (UVP) If any of the MAX17480 output voltages are 400mV below the target voltage, the controller sets the fault latch, shuts down all the SMPSs, and activates the internal passive discharge MOSFET. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. VCC Undervoltage-Lockout (UVLO) Protection If the VCC voltage drops below 4.2V (typ), the controller assumes that there is not enough supply voltage to make valid decisions and sets a fault latch. During a UVLO fault, the controller shuts down all the SMPSs immediately, forces DL and DH low, and pulls CSN1, CSN2, and OUT3 low through internal 20 discharge FETs. If the VCC falls below the POR threshold (1.8V, typ), DL is forced low even if it was previously high due to a latched overvoltage fault. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller.
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VDDIO Undervoltage-Lockout (UVLO) Protection If the VDDIO voltage drops below 0.7V (typ), the controller assumes that there is not enough supply voltage to make valid decisions and sets a UV fault latch. During VDDIO UVLO, as with UVP, the controller shuts down all the SMPSs immediately, forces DL and DH low, and pulls CSN1, CSN2, and OUT3 low through internal 20 discharge FETs. If the VCC falls below the POR threshold (1.8V, typ), DL is forced low even if it was previously high due to a latched overvoltage fault. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. Thermal Fault Protection The MAX17480 features a thermal fault protection circuit. When the junction temperature rises above +160C, a thermal sensor sets the fault latch and shuts down immediately, forcing DH and DL low and turning on the 20 discharge FETs for all SMPSs. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller after the junction temperature cools by 15C.
Other Fault Protection (Nonlatched)
VIN3 Undervoltage-Lockout (UVLO) Protection If the VIN3 voltage drops below 2.5V (typ), the controller assumes that there is not enough input voltage for NB SMPSs. If VIN3 UVLO happens before or just after softstart, the NB SMPS is disabled and the internal target voltage stays off. When the VIN3 subsequently rises past its UVLO rising threshold 2.6V (typ), NB goes through the soft-start sequence with a 1mV/s slew rate. If VIN3 UVLO happens while the MAX17480 is running, the NB SMPS is stopped, the NB target is reset to 0 immediately, and PWRGD is forced low. When VIN3 subsequently rises above the UVLO rising threshold 2.6V (typ), the NB SMPS restarts with 1mV/s slew rate to the previous DAC target.
Core SMPS MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications where a large VIN - VOUT differential exists. The high-side gate drivers (DH) source and sink 2.2A, and the low-side gate drivers (DL) source 2.7A and sink 8A. This ensures robust gate drive for high-current applications. The DH floating high-side MOSFET drivers are powered by internal boost switch charge pumps at BST, while the DL synchronous-rectifier drivers are powered directly by the 5V bias supply (VDD).
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AMD 2-/3-Output Mobile Serial VID Controller
Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17480 interprets the MOSFET gates as "off" while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL low is robust, with a 0.25 (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces could require rising LX edges that do not pull up the low-side MOSFET's gate, causing shoot-through currents. The capacitive coupling between LX and DL created by the MOSFET's gate-todrain capacitance (CRSS), gate-to-source capacitance (CISS - CRSS), and additional board parasitics should not exceed the following minimum threshold: C VGS(TH) > VIN RSS CISS Typically, adding a 4700pF capacitor between DL and power ground (CNL in Figure 11), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. Alternatively, shoot-through currents can be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5 in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (R BST in Figure 11). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise. enabled, setting the PSI_L bit to 0 disables the offset, reducing power consumption in the low-power state. See the Core SMPS Offset section for a detailed description of this feature. In addition, the address of the core SMPSs can be exchanged, allowing for flexible layout of the MAX17480 with respect to the CPU placement on the same or opposite sides of the PCB. Table 5 shows the OPTION pin voltage levels and the features that are enabled.
MAX17480
MAX17480
BST DH LX
(RBST)* INPUT (VIN) CBST NH L
VDD
CBYP
DL NL (CNL)* PGND
(RBST)* OPTIONAL--THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL--THE CAPACITOR REDUCES LX-TO-DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 11. Gate-Drive Circuit
Table 5. OPTION Pin Settings
OPTION VCC 3.3V 2V GND OFFSET ENABLES 0 0 1 1 SMPS1 ADDRESS BIT 1 (VDD0) BIT 2 (VDD1) BIT 1 (VDD0) BIT 2 (VDD1) SMPS2 ADDRESS BIT 2 (VDD1) BIT 1 (VDD0) BIT 2 (VDD1) BIT 1 (VDD0)
Offset and Address Change for Core SMPSs (OPTION)
The +12.5mV offset and the address change features of the MAX17480 can be selectively enabled and disabled by the OPTION pin setting. When the offset is
Note: VDD0 refers to CORE0 and VDD1 refers to CORE1 for the AMD CPU.
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
Table 6. ILIM3 Setting
ILIM3 VCC GND PEAK CURRENT LIMIT (A) 5.25 4.25 SKIP CURRENT LIMIT (A) 1.3 1.05 MAX DC CURRENT (A) 4.75 3.75 FULL-LOAD DROOP (mV) -26.13 -20.63 OFFSET (mV) 12.5 12.5
Offset and Current-Limit Setting for NB SMPS (ILIM3)
The offset and current-limit settings of the NB SMPS can be set by the ILIM3 pin setting. Table 6 shows the ILIM3 pin voltage levels and the corresponding settings for the offset and current limit of the NB SMPS. The NB offset is always present regardless of PSI_L setting. The I LX3MIN minimum current-limit threshold in skip mode is precisely 25% of the corresponding positive current-limit threshold.
* Core Switching Frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. When selecting a switching frequency, the minimum on-time at the highest input voltage and lowest output voltage must be greater than the 150ns (max) minimum on-time specification in the Electrical Characteristics table: VOUT(MIN)/VIN(MAX) x tSW > tON(MIN) A good rule is to choose a minimum on-time of at least 200ns. When in pulse-skipping operation (PSI_L = 0), the minimum on-time must take into consideration the time needed for proper skip-mode operation. The ontime for a skip pulse must be greater than the 170ns (max) minimum on-time specification in the Electrical Characteristics table: tON(MIN) LVIDLE RSENSE VIN(MAX) - VOUT(MIN)
SMPS Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input Voltage Range: The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. * Maximum Load Current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) x 80%. For multiphase systems, each phase supports a fraction of the load, depending on the current balancing. When properly balanced, the load current is evenly distributed among each phase: I ILOAD(PHASE) = LOAD PH where PH is the total number of active phases.
(
)
* Inductor Operating Point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current.
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AMD 2-/3-Output Mobile Serial VID Controller
Core SMPS Design Procedure
Core Inductor Selection By design, the AMD mobile serial VID application should regard each of the MAX17480 SMPSs as independent, single-phase SMPSs. The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: V VIN - VOUT OUT L= f I SW LOAD(MAX)LIR VIN
where ILOAD(MAX) is the maximum current per phase, and fSW is the switching frequency per phase. Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. If using a swinging inductor (where the inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For the selected inductance value, the actual peak-to-peak inductor ripple current (IINDUCTOR) is defined by: V (V - V ) IINDUCTOR = OUT IN OUT VINfSWL Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): I LOAD(MAX) I IPEAK = + INDUCTOR PH 2 where RSENSE is the resistance value of the currentsense element (inductors' DCR or current-sense resistor), and ILIMIT(PK) is the desired peak current limit (per phase). The peak current-limit threshold voltage adjustment range is from 10mV to 50mV.
MAX17480
Core Output Capacitor Selection The output filter capacitor must have low enough ESR to meet output ripple and load-transient requirements. In CPU VCORE converters and other applications where the output is subject to large load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: VSTEP (RESR + RPCB ) I LOAD(MAX)
In non-CPU applications, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. When operating multiphase systems out-ofphase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage (VRIPPLE) by reducing the total inductor ripple current. For nonoverlapping, multiphase operation (VIN VOUT), the maximum ESR to meet the output-ripple-voltage requirement is: VIN fSW L VRIPPLE RESR ( VIN - VOUT ) VOUT where fSW is the switching frequency per phase. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor selection is usually limited by ESR and voltage rating rather than by capacitance value (this is true of polymer types). The capacitance value required is determined primarily by the output transient-response requirements. Low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the output filter capacitors by a sudden load step. Therefore, the amount of output soar when the load is removed is a function of the output voltage and inductor value. The minimum output capacitance required to prevent overshoot (VSOAR) due to stored inductor energy can be calculated as: COUT
Core Peak Inductor Current Limit (ILIM12) The MAX17480 overcurrent protection employs a peak current-sensing algorithm that uses either currentsense resistors or the inductor's DCR as the currentsense element (see the Current Sense section). Since the controller limits the peak inductor current, the maximum average load current is less than the peak current-limit threshold by an amount equal to half the inductor ripple current. Therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and input-to-output voltage difference. When combined with the output undervoltage-protection circuit, the system is effectively protected against excessive overload conditions.
The peak current-limit threshold is set by the voltage difference between ILIM and REF using an external resistor-divider: VCS(PK) = VCSP_ - VCSN_ = 0.052 x (VREF - VILIM12) ILIMIT(PK) = VCS(PK)/RSENSE
(I LOAD(MAX) )
2
L
2VOUT VSOAR
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem.
Core Input Capacitor Selection The input capacitor must meet the ripple-current requirement (IRMS) imposed by the switching currents. For a dual 180 interleaved controller, the out-of-phase operation reduces the RMS input ripple current, effectively lowering the input capacitance requirements. When both outputs operate with a duty cycle less than 50% (VIN > 2VOUT), the RMS input ripple current is defined by the following equation:
I RMS = VOUT1 VOUT2 V IOUT1 (IOUT1 - I IN ) + V I OUT2(IOUT2 - I IN )
IN IN
Core Transient Droop and Stability The inductor current ripple sensed across the currentsense inputs (CSP_ - CSN_) generates a proportionate current out of the FBAC pin. This AC current flowing across the effective impedance at FBAC generates an AC ripple voltage. Actual stability, however, depends on the AC voltage at the FBDC pin, and not on the FBAC pin. Based on the configuration shown in Figure 5, the ripple voltage at the FBDC pin can only be less than, or equal to, the ripple at the FBAC pin. With the requirement that R FBDC = R FBAC , and (ZCFB//RFB) < 10% of RFBAC, then:
RFBAC = RFBDC 1 COUT fSWRSENSE _ Gm(FBAC)
where IIN is the average input current: V V I IN = OUT1 IOUT1 + OUT2 IOUT2 VIN VIN In combined mode (GNDS1 = V DDIO or GNDS2 = VDDIO) with both phases active, the input RMS current simplifies to: V 1 V IRMS = IOUT OUT - OUT VIN VIN 2 For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the MAX17480 is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit longevity.
where Gm(FBAC_) is typically 2mS as defined in the Electrical Characteristics table, RSENSE_ is the effective value of the current-sense element that is used to provide the (CSP_, CSN_) current-sense voltage, and fSW is the selected switching frequency. Based on the above requirement for RFBAC and RFBDC, and with the other requirement for RFBDC defined in the Core Steady-State Voltage Positioning (DC Droop) section, RFBAC and RFBDC can be chosen. The resultant AC droop is: R R R RDROOP _ AC FBDC FBAC SENSE Gm(FBAC) RFBAC + RFBDC Capacitor CFB is required when the RDROOP_DC is less than RDROOP_AC. Choose CFB according to the following equation: CFB x RFB / /(RFBAC + RFBDC ) = 3 x tSW
Core Voltage Positioning and Loop Compensation Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor's power-dissipation requirements. The controller uses a transconductance amplifier to set the transient AC and DC output-voltage droop (Figure 5). The FBAC and FBDC configuration adjusts the steady-state regulation voltage as a function of the load. This adjustability allows flexibility in the selected current-sense resistor value or inductor DCR, and allows smaller current-sense resistance to be used, reducing the overall power dissipated.
Core Steady-State Voltage Positioning With R DROOP_AC defined, the steady-state voltagepositioning slope, RDROOP_DC, can only be less than, or at most equal to, RDROOP_AC:
RDROOP _ DC = RFBDCRFBACRSENSE Gm(FBAC) RFBAC + RFBDC + RFB
Choose the RFBDC and RFBAC already previously chosen, then select RFB to give the desired droop. DC droop is typically used together with the +12.5mV offset feature to keep within the DC tolerance window of the application. See the Offset and Address Change for Core SMPSs (OPTION) section.
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AMD 2-/3-Output Mobile Serial VID Controller
Core Power-MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high-load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-todrain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems might occur (see the Core SMPS MOSFET Gate Drivers section). Core MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage:
V PD (NH Resistive) = OUT ILOAD2RDS(ON) V
IN
rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: : PD (NH Switching) = VIN(MAX)
MAX17480
(
)2 CIRSSfSW ILOAD GATE
where CRSS is the reverse transfer capacitance of NH, IGATE is the peak gate-drive source/sink current (1A, typ), and ILOAD is the per-phase current. Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C x VIN2 x fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage: V I 2 PD (NL Resistive) = 1- OUT LOAD RDS(ON) VIN(MAX) TOTAL The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX), but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, the circuit can be "overdesigned" to tolerate:
I LOAD(MAX)= I PEAK(MAX)- I LOAD(MAX)LIR I INDUCTOR = I PEAK(MAX)- 2 2
where ILOAD is the per-phase current. Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in the high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very
where I PEAK(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good-sized heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current per phase. This diode is optional and can be removed if efficiency is not critical.
Core Boost Capacitors The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1F ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1F. For these applications,
41
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AMD 2-/3-Output Mobile Serial VID Controller MAX17480
select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs' gates: CBST = N x QGATE 200mV
where N is the number of high-side MOSFETs used for one SMPS, and QGATE is the gate charge specified in the MOSFET's data sheet. For example, assume two IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer's data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: 2 x 24nC : CBST = = 0.24F 200mV Selecting the closest standard value, this example requires a 0.22F ceramic capacitor.
NB Peak Inductor Current Limit (ILIM3) The MAX17480 NB regulator overcurrent protection employs a peak current-sensing algorithm that uses the high-side MOSFET RON(NH3) as the current-sense element. Since the controller limits the peak inductor current, the maximum average load current is less than the peak current-limit threshold by an amount equal to half the inductor ripple current. Therefore, the maximum load capability is a function of the current-limit setting, inductor value, switching frequency, and input-to-output voltage difference. When combined with the output undervoltage-protection circuit, the system is effectively protected against excessive overload conditions. The peak current-limit threshold is set by the ILIM3 pin setting (see the Offset and Current-Limit Setting for NB SMPS (ILIM3) section). NB Output Capacitor Selection The output filter capacitor must have low enough ESR to meet output ripple and load-transient requirements. In CPU VCORE converters and other applications where the output is subject to large load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: VSTEP (RESR + RPCB ) : I LOAD(MAX)
The output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. For single-phase operation, the maximum ESR to meet the output-ripple-voltage requirement is: VIN3 fSW 3L3 VRIPPLE3 RESR : ( VIN3 - VOUT3 ) VOUT3 where f SW3 is the switching frequency. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, capacitor selection is usually limited by ESR and voltage rating rather than by capacitance value (this is true of polymer types).
NB SMPS Design Procedure
NB Inductor Selection The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: V VIN3 - VOUT3 OUT3 : L3 = f V SW 3I LOAD3(MAX)LIR IN3
where ILOAD3(MAX) is the maximum current and fSW3 is the switching frequency of the NB regulator. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. If using a swinging inductor (where the inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For the selected inductance value, the actual peak-to-peak inductor ripple current (IINDUCTOR) is defined by: : V (V - VOUT3 ) IINDUCTOR = OUT3 IN3 VIN3 fSW 3L3
Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK3): I I PEAK3 = I LOAD3(MAX)+ INDUCTOR 2
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AMD 2-/3-Output Mobile Serial VID Controller
The capacitance value required is determined primarily by the stability requirements. However, the soar and sag calculations are still provided here for reference. Low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the output filter capacitors by a sudden load step. Therefore, the amount of output soar and sag when the load is applied or removed is a function of the output voltage and inductor value. The soar and sag voltages are calculated as:
VSOAR3
( ILOAD3(MAX) )2 L3 =
2VOUT3COUT3 L3
2
NB Steady-State Voltage Positioning Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor's power-dissipation requirements. For NB, the load line is generated by sensing the inductor current through the high-side MOSFET on-resistance (RON(NH3)), and is internally preset to -5.5mV/A (typ). This guarantees the output voltage to stay in the static regulation window over the maximum load conditions per AMD specifications. See Table 6 for full-load voltage droop according to different ILIM3 settings. NB Transient Droop and Stability The voltage-positioned load-line of the NB SMPS also provides the AC ripple voltage required for stability. To maintain stability, the output capacitive ripple must be kept smaller than the internal AC ripple voltage. Hence, a minimum NB output capacitance is required as calculated below: 1 VOUT3 COUT3 > : 1+ V 2xf xR
SW 3 DROOP3(MIN) IN3
MAX17480
: VSAG3 = 2C
OUT 3 VIN3 x DMAX - VOUT 3
( ILOAD3(MAX) )
(
)
+
I LOAD3(MAX)( tSW 3 - t ) COUT3
where D MAX is the maximum duty cycle of the NB SMPS as listed in the Electrical Characteristics table, tSW3 is the NB switching period programmed by the OSC pin, and t equals VOUT/VIN x tSW when in forcedPWM mode, or L x ILX3MIN/(VIN - VOUT) when in pulseskipping mode. When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem.
where R DROOP3(MIN) is 4mV/A as defined in the Electrical Characteristics table, and f SW3 is the NB switching frequency programmed by the OSC pin.
SVI Applications Information
I2C Bus-Compatible Interface
The MAX17480 is a receive-only device. The 2-wire serial bus (pins SVC and SVD) is designed to attach on a low-voltage I2C-like bus. In the AMD mobile application, the CPU directly drives the bus at a speed of 3.4MHz. The CPU has a push-pull output driving to the VDDIO voltage level. External pullup resistors are not required. When not used in the specific AMD application, the serial interface can be driven to as high as 2.5V, and can operate at the lower speeds (100kHz, 400kHz, or 1.7MHz). At lower clock speeds, external pullup resistors can be used for open-drain outputs. Connect both SVC and SVD lines to VDDIO through individual pullup resistors. Calculate the required value of the pullup resistors using: t : RPULLUP R CBUS where tR is the rise time, and should be less than 10% of the clock period. CBUS is the total capacitance on the bus. The MAX17480 is compatible with the standard SVI interface protocol as defined in the following subsections. Figure 12 shows the SVI bus START, STOP, and data change conditions.
NB Input Capacitor Selection The input capacitor must meet the ripple-current requirement (IRMS) imposed by the switching currents. The IRMS requirements can be determined by the following equation: I : IRMS = LOAD3 VOUT3 ( VIN3 - VOUT3 ) VIN3
The worst-case RMS current requirement occurs when operating with VIN3 = 2VOUT3. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD3. For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. The MAX17480 NB regulator is operated as the second stage of a two-stage power-conversion system. Tantalum input capacitors are acceptable. Choose an input capacitor that exhibits less than 10C temperature rise at the RMS input current for optimal circuit longevity.
______________________________________________________________________________________
43
AMD 2-/3-Output Mobile Serial VID Controller MAX17480
SVD
SVC
S START CONDITION DATA LINE STABLE DATA VALID CHANGE OF DATA ALLOWED
P STOP CONDITION
Figure 12. SVI Bus START, STOP, and Data Change Conditions
DATA OUTPUT BY MASTER
D7
D6
D0
NOT ACKNOWLEDGE DATA OUTPUT BY MAX17480
ACKNOWLEDGE SVC FROM MASTER S START CONDITION 1 CLK1 2 CLK2 8 CLK8 9 CLK9
ACKNOWLEDGE CLOCK PULSE
Figure 13. SVI Bus Acknowledge
Bus Not Busy The SVI bus is not busy when both data and clock lines remain high. Data transfers can be initiated only when the bus is not busy. Figure 13 shows the SVI bus acknowledge. Start Data Transfer (S) Starting from an idle bus state (both SVC and SVD are high), a high-to-low transition of the data (SVD) line while the clock (SVC) is high determines a START condition. All commands must be preceded by a START condition. Stop Data Transfer (P) A low-to-high transition of the SDA line while the clock (SVC) is high determines a STOP condition. All operations must be ended with a STOP condition. Slave Address After generating a START condition, the bus master transmits the slave address consisting of a 7-bit device code (110xxxx) for the MAX17480. Since the MAX17480 is a write-only device, the eighth bit of the
44
slave address is 0. The MAX17480 monitors the bus for its corresponding slave address continuously. It generates an acknowledge bit if the slave address was true and it is not in a programming mode.
SVD Data Valid The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. The device that acknowledges has to pull down the SVD line during the acknowledge clock pulse so that the SVD line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. See Figure 13.
______________________________________________________________________________________
AMD 2-/3-Output Mobile Serial VID Controller
Command Byte A complete command consists of a START condition (S) followed by the MAX17480's slave address and a data phase, followed by a STOP condition (P). For the slave address, bits 6:4 are always 110 and bit 3 is X (don't care). The WR bit should always be 1 since read functions are not supported. Figure 14 is the SVI bus data-transfer summary. Table 7 is a description of the SVI send byte address and Table 8 describes serial VID 8-bit field encoding.
SMPS Applications Information
Duty-Cycle Limits
Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by stability requirements, not the minimum off-time (tOFF(MIN)). The MAX17480 does not include slope compensation, so the controller becomes unstable with duty cycles greater than 50% per phase: VIN(MIN) 2VOUT(MAX) However, the controller can briefly operate with duty cycles over 50% during heavy load transients.
MAX17480
START SLAVE ADDRESS SET DAC AND PSI_L
STOP
S
P
WR (WRITE) = 0
VDD1 (CORE1)
VDD0 (CORE0)
PSI_L
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
FIXED VALUES
Figure 14. SVI Bus Data Transfer Summary
Table 7. SVI Send Byte Address Description
BIT 6:4 3 Always 110b. X--don't care. VDD1, if set then the following data byte contains the VID for VDD1. Bit 2 is ignored in combined mode (GNDS1 or GNDS2 = VDDIO). VDD1 refers to CORE1 of the AMD CPU. DESCRIPTION
ACK
Table 8. Serial VID 8-Bit Field Encoding
BIT DESCRIPTION PSI_L: Power-Save Indicator 0 means the processor is at an optimal load and the SMPS(s) can enter power-saving mode. The SMPS operates in pulse-skipping mode after exiting the boot mode. Offset is disabled if previously enabled by the OPTION pin. The MAX17480 enters 1-phase operation if in combined mode (GNDS1 or GNDS2 = H). 1 means the processor is in a high currentconsumption state. The SMPS operates in forcedPWM mode after exiting the boot mode. Offset is enabled if previously enabled by the OPTION pin. The MAX17480 returns to 2-phase operation if in combined mode (GNDS1 or GNDS2 = H). 6:0 SVID[6:0] as defined in Table 7.
2
7 1 VDD0, if set then the following data byte contains the VID for VDD0 in separate mode, and the unified VDD in combined mode. VDD0 refers to CORE0 of the AMD CPU. VDDNB, if set then the following data byte contains the VID for VDDNB.
0
______________________________________________________________________________________
ACK
NB
X
1
1
0
45
AMD 2-/3-Output Mobile Serial VID Controller
Maximum Input Voltage The MAX17480 controller has a minimum on-time, which determines the maximum input operating voltage that maintains the selected switching frequency. With higher input voltages, each pulse delivers more energy than the output is sourcing to the load. At the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse, resulting in pulse-skipping operation regardless of the operating mode selected by PSI_L. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (VIN(SKIP)): 1 : VIN(SKIP) = VOUT f t SW ON(MIN) where fSW is the per-phase switching frequency set by the OSC resistor, and tON(MIN) is 150ns (max) minus the driver's turn-on delay (DL low to DH high). For the best high-voltage performance, use the slowest switching frequency setting (100kHz per phase, ROSC = 432k).
MAX17480
* Connections for current limiting (CSP, CSN) and voltage positioning (FBS, GNDS) must be made using Kelvin-sense connections to guarantee the currentsense accuracy. Place current-sense filter capacitors and voltage-positioning filter capacitors as close as possible to the IC. * Route high-speed switching nodes and driver traces away from sensitive analog areas (REF, VCC, FBAC, FBDC, OUT3, etc.). Make all pin-strap control input connections (SHDN, PGD_IN, OPTION) to analog ground or VCC rather than power ground or VDD. * Route the high-speed serial-interface signals (SVC, SVD) in parallel, keeping the trace lengths identical. Keep the SVC and SVD away from the high-current switching paths. * Keep the drivers close to the MOSFET, with the gatedrive traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require lowimpedance gate drivers to avoid shoot-through currents. * When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET rather than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 15). If possible, mount all the power components on the top side of the board with their ground terminals flush against one another, and mount the controller and analog components on the bottom layer so the internal ground layers shield the analog components from any noise generated by the power components. Follow these guidelines for good PCB layout: * Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. * Connect all analog grounds to a separate solid copper plane; then connect the analog ground to the GND pins of the controller. The following sensitive components connect to analog ground: V CC and VDDIO bypass capacitors, remote sense and GNDS bypass capacitors, and the resistive connections (ILIM12, OSC, TIME). * Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCB (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty.
46
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, C IN, COUT, and DL anode). If possible, make all these connections on the top layer with wide, copperfilled areas. For the NB SMPS, place CIN3 and L3 as near as possible to the MAX17480, using multiple vias to reduce inductance when connecting the different layers. 2) Use multiple vias to connect the exposed backside to the power ground plane (PGND) to allow for a lowimpedance path for the SMPS3 internal low-side MOSFET. 3) Mount the MAX17480 close to the low-side MOSFETs. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the driver IC). 4) Group the gate-drive components (BST capacitors, V DD bypass capacitor) together near the MAX17480.
______________________________________________________________________________________
AMD 2-/3-Output Mobile Serial VID Controller
5) Make the DC-DC controller ground connections as shown in the standard application circuit (Figure 2). This diagram can be viewed as having three separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND, V DD bypass capacitor, and driver IC ground connection go; and the controller's analog ground plane, where sensitive analog components, the MAX17480's AGND pin, and VCC bypass capacitor go. The controller's analog ground plane (AGND) must meet the power ground plane (PGND) only at a single point directly beneath the IC. The power ground plane should connect to the high-power output ground with a short, thick metal trace from PGND to the source of the low-side MOSFETs (the middle of the star ground). 6) Connect the output power planes (VCORE, VOUT3, and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical.
MAX17480
SPLIT CORE CPU SOCKET VDDNB
VCORE0
VCORE1
COUT COUT
CVDD
COUT COUT KELVIN-SENSE VIAS UNDER THE INDUCTOR (REFER TO EVALUATION KIT)
CVCC
CSP CSN CEQ
INDUCTOR
INDUCTOR
RNTC R2 R1
CSP CSN
+
CIN3
KELVIN-SENSE VIAS TO INDUCTOR PAD L3 CIN CIN POWER GROUND INDUCTOR DCR SENSING CIN AGND PIN CIN
COUT3 CONNECT THE EXPOSED PAD TO POWER GND USING MULTIPLE VIAS
Figure 15. PCB Layout Example
______________________________________________________________________________________ 47
AMD 2-/3-Output Mobile Serial VID Controller MAX17480
Pin Configuration
VRHOT BST1 BST2 DH1 VDD
Chip Information
TRANSISTOR COUNT: 24,311 PROCESS: BiCMOS
TOP VIEW
30 29 28 27 26 25 24 23 22 21 THRM 31 VCC 32 CSP1 33 CSN1 34 FBDC1 35 FBAC1 36 GNDS1 37 OPTION 38 OSC 39 TIME 40 1 ILIM12 2 ILIM3 3 IN3 4 IN3 5 LX3 6 LX3 7 BST3 8 SHDN 9 OUT3 10 AGND 20 PWRGD 19 PGD_IN 18 CSP2 17 CSN2 16 FBDC2
DH2
DL1
DL2
LX1
LX2
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 40 TQFN-EP PACKAGE CODE T4055-2 DOCUMENT NO. 21-0140
MAX17480 PGND +
*EP
15 FBAC2 14 GNDS2 13 VDDIO 12 SVC 11 SVD
THIN QFN (5mm x 5mm)
*EXPOSED PAD.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
48 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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